Question

我想弄清楚下面这段代码有什么问题。然而，当我尝试编译此文件时，每个其他文件都有效。

# Error: COMP96_0019: file_io.vhd : (30, 6): Keyword 'begin' expected.
# Error: COMP96_0016: file_io.vhd : (30, 11): Design unit declaration expected.

错误适用于以下所示的细分。

data : in std_logic_vector(63 downto 0);
initial_addr:in std_logic_vector(3 downto 0);
rst_iar_bar:in std_logic; 
clk:in std_logic;
wb_data:out std_logic_vector(63 downto 0);

----fetch
instruction:out std_logic_vector(15 downto 0);

----IDRD
idrd_srcA,idrd_srcB,idrd_data:out std_logic_vector(63 downto 0);
idrd_opcode,idrd_rd_addr,idrd_rs2_addr:out std_logic_vector(3 downto 0);

idrd_addorsub,idrd_lv,idrd_alu_op,idrd_B_select,idrd_saturate,idrd_reg_wr:out std_logic;
idrd_sel: out std_logic_vector(6 downto 0);

----IFID
ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,ifid_rd_addr:out std_logic_vector(3 downto 0)

以下是完整文件，我需要弄清楚如何修复此错误！我正在关注一个由我的教授创建的例子，但是它对我不起作用。

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use std.textio.all;     
use ieee.numeric_std.all;  
use txt_util.all;

entity fileio is
end fileio;


architecture fileio of fileio is
signal data:std_logic_vector(63 downto 0);
signal initial_addr,idrd_rs2_addr,idrd_rd_addr,idrd_opcode,ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,
ifid_rd_addr:std_logic_vector(3 downto 0);
signal reset: std_logic;    -- 

signal Instr_out: std_logic_vector(15 downto 0);


signal clk: std_logic;  --  
signal idrd_addorsub,idrd_lv,idrd_alu_op,idrd_saturate,idrd_B_select,idrd_reg_wr:std_logic;
signal instruction_in:std_logic_vector(15 downto 0);
signal wb_data,idrd_srcA,idrd_srcB,idrd_data: std_logic_vector(63 downto 0); 
signal idrd_sel:std_logic_vector(6 downto 0);
signal instruction:std_logic_vector(15 downto 0);
constant period:time:=20ns;     


    data : in std_logic_vector(63 downto 0);
    initial_addr:in std_logic_vector(3 downto 0);
    rst_iar_bar:in std_logic; 
    clk:in std_logic;
    wb_data:out std_logic_vector(63 downto 0);

    ----fetch
    instruction:out std_logic_vector(15 downto 0);

    ----IDRD
    idrd_srcA,idrd_srcB,idrd_data:out std_logic_vector(63 downto 0);
    idrd_opcode,idrd_rd_addr,idrd_rs2_addr:out std_logic_vector(3 downto 0);
    idrd_addorsub,idrd_lv,idrd_alu_op,idrd_B_select,idrd_saturate,idrd_reg_wr:out std_logic;
    idrd_sel: out std_logic_vector(6 downto 0);

    ----IFID
    ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,ifid_rd_addr:out std_logic_vector(3 downto 0);




begin                 
uut:cellliteunit 
port map(
    instruction=>instruction,
    idrd_srcA=>idrd_srcA,
    idrd_srcB=>idrd_srcB,
    idrd_data=>idrd_data,
    idrd_opcode=>idrd_opcode,
    idrd_rd_addr=>idrd_rd_addr, 
    idrd_rs2_addr=>idrd_rs2_addr,
    idrd_addorsub=>idrd_addorsub,idrd_lv=>idrd_lv,idrd_alu_op=>idrd_alu_op,
    idrd_B_select=>idrd_B_select,idrd_saturate=>idrd_saturate,idrd_reg_wr=>idrd_reg_wr, 
    idrd_sel=>idrd_sel,
    ifid_opcode=>ifid_opcode,ifid_rs1_addr=>ifid_rs1_addr,
    ifid_rs2_addr=>ifid_rs2_addr,ifid_rd_addr=>ifid_rd_addr,
    data=>data,
    initial_addr=>initial_addr,
    rst_iar_bar=>rst_iar_bar,
    clk=>clk,
    wb_data=>wb_data
    );       

a:process       
begin
    data<=X"FFFFFFFFFFFFFFFF"; 
    wait for 6*period;

    data<=X"0000000100000000";

    wait;
end process;

b:process
begin    
    initial_addr<=X"0";

    rst_iar_bar<='0', '1' after period;
    wait;
end process b;

clock:process
begin
    clk<='1';
    for i in 0 to 100 loop
        wait for period;
        clk<=not clk;
    end loop;
    wait;
end process clock;  


write_p:process
    file outfile:text;          
    variable r:string(1 to 5);
    variable s:string(1 to 5);
    variable t:string(1 to 5);

begin                
    for j in 1 to 15 loop
        wait for 2*period;
        case instruction(15 downto 12) is
            ...
            ...
            ...
        end case;
    end loop;
end fileio;

Answer 1

您在帖子中显示的细分不属于架构。 data : in std_logic_vector(63 downto 0);等是端口声明（注意方向说明符in）。我认为这是cellliteunit的实体声明中的复制和粘贴错误。

另请注意，此块中的每个标识符已经提供给完全相同类型的体系结构中的信号。没有你所有的其他文件，我无法测试这个，但我认为你只需要从29到45行删除该块。

修改您的体系结构中缺少组件声明。从第29行到第45行的街区似乎就是这样。它可能应该像这样：

component cellliteunit port( data : in std_logic_vector(63 downto 0); initial_addr:in std_logic_vector(3 downto 0); [...] ifid_opcode,ifid_rs1_addr,ifid_rs2_addr,ifid_rd_addr:out std_logic_vector(3 downto 0) ); end component

有源VHDL：预期的设计单元声明

1 个答案: