Question

我不知道为什么vivado在我的信号声明上抛出语法错误，有人看到我看不到的东西吗？我试图将其移动，但无济于事。没有它，我唯一的错误就是尝试从输出分配某些内容的错误。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity myip_v1_0 is
    generic (
        -- Users to add parameters here

        -- User parameters ends
        -- Do not modify the parameters beyond this line


        -- Parameters of Axi Slave Bus Interface S_AXIS
        C_S_AXIS_TDATA_WIDTH    : integer   := 32;

        -- Parameters of Axi Master Bus Interface M_AXIS
        C_M_AXIS_TDATA_WIDTH    : integer   := 32;
        C_M_AXIS_START_COUNT    : integer   := 32
    );
    port (
        -- Users to add ports here
        FRAME_SIZE : in std_logic_vector(7 downto 0);
        EN          : in std_logic;
        AXI_EN      :IN STD_LOGIC;
        -- User ports ends
        -- Do not modify the ports beyond this line


        -- Ports of Axi Slave Bus Interface S_AXIS
        s_axis_aclk : in std_logic;
        s_axis_aresetn  : in std_logic;
        s_axis_tready   : out std_logic;
        s_axis_tdata    : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
        s_axis_tstrb    : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
        s_axis_tlast    : in std_logic;
        s_axis_tvalid   : in std_logic;

        -- Ports of Axi Master Bus Interface M_AXIS
        m_axis_aclk : in std_logic;
        m_axis_aresetn  : in std_logic;
        m_axis_tvalid   : out std_logic;
        m_axis_tdata    : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
        m_axis_tstrb    : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
        m_axis_tlast    : out std_logic;
        m_axis_tready   : in std_logic

    );


end myip_v1_0;

architecture arch_imp of myip_v1_0 is
    -- component declaration


    component myip_v1_0_S_AXIS is
        generic (
        C_S_AXIS_TDATA_WIDTH    : integer   := 32
        );
        port (
        S_AXIS_ACLK : in std_logic;
        S_AXIS_ARESETN  : in std_logic;
        S_AXIS_TREADY   : out std_logic;
        S_AXIS_TDATA    : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
        S_AXIS_TSTRB    : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
        S_AXIS_TLAST    : in std_logic;
        S_AXIS_TVALID   : in std_logic
        );
    end component myip_v1_0_S_AXIS;

    component myip_v1_0_M_AXIS is
        generic (
        C_M_AXIS_TDATA_WIDTH    : integer   := 32;
        C_M_START_COUNT : integer   := 32
        );
        port (
        M_AXIS_ACLK : in std_logic;
        M_AXIS_ARESETN  : in std_logic;
        M_AXIS_TVALID   : out std_logic;
        M_AXIS_TDATA    : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
        M_AXIS_TSTRB    : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
        M_AXIS_TLAST    : out std_logic;
        M_AXIS_TREADY   : in std_logic
        );
    end component myip_v1_0_M_AXIS;

这怎么不正确？

    signal m_axis_tvalidw   : out std_logic_vector;
    signal m_axis_tdataw    : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
    signal m_axis_tstrbw    : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
    signal m_axis_tlastw    : out std_logic;

begin

-- Instantiation of Axi Bus Interface S_AXIS
myip_v1_0_S_AXIS_inst : myip_v1_0_S_AXIS
    generic map (
        C_S_AXIS_TDATA_WIDTH    => C_S_AXIS_TDATA_WIDTH
    )
    port map (
        S_AXIS_ACLK => s_axis_aclk,
        S_AXIS_ARESETN  => s_axis_aresetn,
        S_AXIS_TREADY   => s_axis_tready,
        S_AXIS_TDATA    => s_axis_tdata,
        S_AXIS_TSTRB    => s_axis_tstrb,
        S_AXIS_TLAST    => s_axis_tlast,
        S_AXIS_TVALID   => s_axis_tvalid
    );

-- Instantiation of Axi Bus Interface M_AXIS
myip_v1_0_M_AXIS_inst : myip_v1_0_M_AXIS
    generic map (
        C_M_AXIS_TDATA_WIDTH    => C_M_AXIS_TDATA_WIDTH,
        C_M_START_COUNT => C_M_AXIS_START_COUNT
    )
    port map (
        M_AXIS_ACLK     => m_axis_aclk,
        M_AXIS_ARESETN  => m_axis_aresetn,
        M_AXIS_TVALID   => m_axis_tvalid,
        M_AXIS_TDATA    => m_axis_tdata,
        M_AXIS_TSTRB    => m_axis_tstrb,
        M_AXIS_TLAST    => m_axis_tlast,
        M_AXIS_TREADY   => m_axis_tready
    );

由于未输出其他抛出错误，因此未发出信号。

    -- Add user logic here
    --MULTIPLEXER
     m_axis_tdata <= S_AXIS_TDATA WHEN (AXI_EN='1') ELSE
     M_AXIS_TDATAW;

     m_axis_tSTRB <= S_AXIS_TSTRB WHEN (AXI_EN='1') ELSE
     M_AXIS_TSTRBW;

     m_axis_tLAST <= S_AXIS_TLAST WHEN (AXI_EN='1') ELSE
     M_AXIS_TLASTW;

     m_axis_TVALID <= S_AXIS_TVALID WHEN (AXI_EN='1') ELSE
     M_AXIS_TVALIDW;

    -- User logic ends

end arch_imp;

Answer 1

信号没有模式，例如in，out或inout。

所有对象都需要完全约束，但是信号m_axis_tvalidw的声明类型不受约束。您需要指定范围约束。

VHDL信号声明有麻烦吗？

1 个答案: