Question

我有一个正常工作的systemc代码，如下所示，我正在尝试将其转换为系统Verilog，并在systemverilog代码中看到一些错误

typedef int token_type;
struct packet
{
    int src_x, src_y;
    int dest_x, dest_y;
    token_type token;

    packet(int sx = -1, int sy = -1, int dx = -1, int dy = -1,
    token_type t = token_type())
    : src_x(sx), src_y(sy), dest_x(dx), dest_y(dy), token(t)
    {
    }

    bool operator==(const packet &x) const
    {
        return (x.src_x == src_x) && (x.src_y == src_y)
        && (x.dest_x == dest_x) && (x.dest_y == dest_y)
        && (x.token == token);
    }
};

std::ostream &operator<<(std::ostream &o, const packet &p);

SC_MODULE(router)
{
    sc_in<bool> clock; 
    enum { PE = 0, PORTS };
    sc_in<packet> port_in[PORTS]; 
    sc_out<packet> port_out[PORTS]; 

    void main(); 

    SC_CTOR(router)
    : x_(-1), y_(-1)
    {
        SC_METHOD(main);
        sensitive << clock.pos();
    }

    void set_xy(int x, int y);
    protected:
    std::list<packet> out_queue_[PORTS];
    int x_, y_; 
};

我在上面的另一个文件中调用上面的函数

std::ostream &operator<<(std::ostream &o, const packet &p)
{
    char buf[100];
    return o << buf << ", " << p.token;
}

void router::main()
{
    assert((x_ != -1) && (y_ != -1)); // to identify PE
}

void router::set_xy(int x, int y)
{
    assert((x_ == -1) && (y_ == -1)); 
    assert((x != -1) && (y != -1)); 

    x_ = x;
    y_ = y;
}

我试图编写的系统Verilog如下所示，尽管我正在努力找出它需要帮助。我看到的错误在我看到

的行上提到

typedef int token_type;
class pkt;
int src_x, src_y;
int dest_x, dest_y;
token_type token;

function new(int sx = -1, int sy = -1, int dx = -1, int dy = -1,
    token_type t);

    this.src_x=sx; this.src_y=sy;
    this.dest_x=dx; this.dest_y=dy; 
    this.token=t;

endfunction
function logic operator(pkt x);
    return (x.src_x == src_x) && (x.src_y == src_y)
        && (x.dest_x == dest_x) && (x.dest_y == dest_y)
        && (x.token == token);
endfunction
endclass
pkt packet; 


module router(clock,port_in,port_out);
input clock;
enum { PE = 0, PORTS } ports;   

input [0:packet]  port_in[0:PORTS];//error illegal reference to class packet,range must be bounded by constant expressions.
output [0:packet] port_out[0:PORTS];
int x_, y_;

always @(posedge clock)
begin
    assert((x_ != -1) && (y_ != -1));
end

endmodule

如何在系统Verilog中使用范围来使这段代码有效？具体来说，我希望在系统Verilog中定义struct packet中的数据包，它在SystemC代码中完成相同的模式

如何使用系统结构枚举将代码转换为系统verilog

0 个答案: