BLOCKRAM.BMM

Question

我有一个使用以下参数生成的BLOCK RAM（单端口ram）：

Memory Type: Single Port RAM 
Write Enable: Use Byte Write Enable =  Disabled 
Write/Read Width = 32 
Write/Read depth = 131072

它工作正常。现在我想写一个单独的字节，例如字节0,1,2或3相对于32位字。如何使用块ram进行字节写访问来实现此目的。我尝试了以下方法，但它无法读出或写入任何数据（32位也不是8位）。

Memory Type: Single Port RAM
Write Enable: Use Byte Write Enable = Yes,
Byte Size :8
Write/Read Width = 32
Write/Read depth = 131072

在第一种情况下，写信号是：

we     <= "1" when (not(datarw_cpu = '0') and  datareq_mem = '1' ) else "0";

并且在第二种情况下，写使能是：

we <= "1111" when (not(datarw_cpu = '0') and datareq_mem = '1' ) else "0000";

任何人都可以帮忙。

BLOCKRAM.BMM

ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff]
BUS_BLOCK
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
    BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
END_ADDRESS_SPACE;

ADDRESS_SPACE pr_mem2 RAMB32 [0x00010000:0x0008ffff]
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[120].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[112].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[104].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[96].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[88].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[80].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[72].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[64].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[56].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[48].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[40].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[32].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[24].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[16].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[121].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[113].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[105].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[97].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[89].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[81].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[73].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[65].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[57].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[49].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[41].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[33].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[25].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[17].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[122].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[114].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[106].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[98].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[90].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[82].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[74].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[66].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[58].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[50].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[42].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[34].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[26].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[18].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[123].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[115].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[107].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[99].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[91].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[83].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[75].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[67].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[59].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[51].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[43].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[35].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[27].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[19].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[124].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[116].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[108].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[100].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[92].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[84].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[76].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[68].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[60].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[52].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[44].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[36].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[28].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[20].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[12].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[125].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[117].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[109].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[101].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[93].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[85].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[77].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[69].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[61].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[53].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[45].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[37].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[29].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[21].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[13].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[5].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[126].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[118].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[110].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[102].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[94].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[86].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[78].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[70].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[62].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[54].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[46].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[38].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[30].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[22].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[6].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
    BUS_BLOCK
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[127].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [31:30];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[119].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [29:28];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[111].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [27:26];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[103].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [25:24];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[95].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [23:22];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[87].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [21:20];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[79].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [19:18];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[71].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [17:16];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[63].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [15:14];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[55].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [13:12];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[47].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [11:10];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[39].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [9:8];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[31].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [7:6];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[23].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [5:4];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[15].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [3:2];
        BRAM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/v5_noinit.ram/SP.SINGLE_PRIM36.SP [1:0];
    END_BUS_BLOCK;
END_ADDRESS_SPACE;

非常感谢。

如何在32位宽的Block RAM

BLOCKRAM.BMM

0 个答案: