Question

我是veriloghdl的新手，我在verilog hdl中收到此错误

Error (10170): Verilog HDL syntax error at TrafficLight.v(59) near text "endcase";  expecting "end"

谁能告诉我出了什么问题？

我的代码是

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;
always@(posedge clk)
    begin
    case(state)
        3'b000:
            if(tt < 5)
                next_state = s0;
            else
                begin
                next_state = s1;
                assign out [5:0] = 6'b100001;
                end
        3'b001:
            if(tt < 1)
                next_state = s1;
            else
            begin
                next_state = s2;
                assign out [5:0] = 6'b010001;
            end
        3'b010:
            if(tt < 1)
                next_state = s2;
            else
            begin
                next_state = s3;
                assign out [5:0] = 6'b001001;
            end
        3'b011:
            if(tt < 5)
                next_state = s3;
            else
            begin
                next_state = s4;
                assign out [5:0] = 6'b001100;
            end
        3'b100:
            if(tt < 1)
                next_state = s4;
            else
            begin
                next_state = s5;
                assign out [5:0] = 6'b001010;
            end
        3'b101:
            if(tt < 1)
                next_state = s0;
            else
                begin
                next_state = s5;
                assign out [5:0] = 6'b001001;
                end
    endcase


    always@(posedge clk);
        begin
        state = next_state;
        tt = tt - 1;
        end

endmodule

我发现错误发生在行endcase和endmodule上。我想我必须用某些东西关闭它们。

Answer 1

您的代码中存在一些错误 -

你错过了＆＃34;结束＆＃34;在＆＃34; endcase＆＃34;之后声明。 case语句之前的begin块需要结束。

您已添加＆＃34;;＆＃34;在always块声明中。

always@(posedge clk);
    begin
    state = next_state;
    tt = tt - 1;
    end

不需要＆＃34;;＆＃34;在总是阻止。

module TrafficLight(t, state, next_state, clk, out);

input t, clk;
output out;
localparam s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100, s5=3'b101;
reg[2:0] state, next_state, tt;

在上面的代码片段中，我看到你添加了＆＃34; state＆＃34;和＆＃34; next_state＆＃34;作为模块的端口，但没有为它们分配任何方向。将它们作为端口删除或将它们作为＆＃34;输入＆＃34;或＆＃34;输出＆＃34;。

您还需要删除＆＃34;分配＆＃34;驾驶出局时的声明。因为它在一个程序块内，你不需要＆＃34;分配＆＃34;这里。

您可以找到代码here

的所有更新

错误（10170）：TrafficLight.v（59）附近文本“endcase”的Verilog HDL语法错误;期待“结束”

1 个答案: