错误（10170）：lab2.v（19）附近文本“if”时的Verilog HDL语法错误;期待一个操作数

Question

使用2014版Quartus II软件（网络版），编译以下代码时收到错误10170：

module lab2 (A,B,Select,Numout);         
    input [3:0] A;
    input [3:0] B;          
    input [2:0] Select;     
    output [7:0] Numout;    

    reg [7:0] Numout;       

    reg [7:0] add_result, sub_result, mul_result, div_result;
    reg [7:0] min_result, max_result, ave_result, all_on_result;


    always @ (A,B)
    begin              
        add_result = A + B;
        sub_result = A - B;
        mul_result = A * B;
        div_result = A / B;
        **min_result = reg Numout;**

                         always @ (A,B)
                         begin
                             if (A>B)
                             begin
                                 Numout = B;
                             end
                             else if (B>A)
                             begin  
                                 Numout = A;
                             end
                             else if (A==B)
                             begin
                                 Numout = A;
                             end    
                         end    
        max_result = ~min_result;
        ave_result = (A + B)/2;

        //*******************************************************************
        //ADD EXTRA CODE HERE TO CALCULATE:
        //      min_result, max_result, ave_result, all_on_result
        //*******************************************************************
    end

    always @ (Select, add_result, sub_result, mul_result, div_result, min_result, max_result, ave_result, all_on_result)
    begin
        case (Select)
            3'b000: Numout = add_result;        
            3'b001: Numout = sub_result;        
            3'b010: Numout = mul_result;
            3'b011: Numout = min_result;
            3'b100: Numout = max_result;    
            3'b101: Numout = ave_result;
            3'b110: Numout = all_on_result;
        endcase

    end                     

endmodule

收到错误：

  

错误（10170）：lab2.v（19）附近文本“if”时的Verilog HDL语法错误;   期待操作数