VHDL-实施LFSR

Question

我写下了Vhdl代码＆amp;用于在ISE上实现LFSR的testbench代码。 我在ISE上从这条路径中获取LFSR代码。 语言模板 - VHDL - 综合结构 - 编码示例--- 计数器--- LFSR

我的问题是在simulink（isim），我总是面对＆＃39; U＆＃39;签署out_lfsr。 你能帮助我吗？

vhdl代码：

    library IEEE;
        use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;



entity lfsr is

port(rst,clk,clk_en:in std_logic;
out_lfsr: inout std_logic_vector(31 downto 0);
init_value:in std_logic_vector(31 downto 0)
);

end lfsr;

architecture Behavioral of lfsr is


begin

process(clk)
begin
   if ( clk'event and clk ='1') then
      if (rst = '1') then
         out_lfsr <= init_value;
      elsif clk_en='1' then 
         out_lfsr(31 downto 1) <= out_lfsr(30 downto 0) ;
         out_lfsr(0) <= not(out_lfsr(31) XOR out_lfsr(21) XOR out_lfsr(0)); 
      end if;
   end if;
end process; 


end Behavioral;

测试平台：

    LIBRARY ieee;
USE ieee.std_logic_1164.ALL;



ENTITY tb_lfsr IS
END tb_lfsr;

ARCHITECTURE behavior OF tb_lfsr IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT lfsr
    PORT(
         rst : IN  std_logic;
         clk : IN  std_logic;
         clk_en : IN  std_logic;
         out_lfsr : INOUT  std_logic_vector(31 downto 0);
         init_value : IN  std_logic_vector(31 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal rst : std_logic := '0';
   signal clk : std_logic := '0';
   signal clk_en : std_logic := '1';
   signal init_value : std_logic_vector(31 downto 0) := (others => '1');

    --Outputs
   signal out_lfsr : std_logic_vector(31 downto 0):=(others => '0');

   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: lfsr PORT MAP (
          rst => rst,
          clk => clk,
          clk_en => clk_en,
          out_lfsr => out_lfsr,
          init_value => init_value
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;



END;

Answer 1

您必须在其他模块中重置此模块才能使其正常工作。重置时，它会将输入值加载到输出。

reset_p: process begin
    rst <= '1';
    wait for 10 * clk_period;
    rst <= '0';
    wait;
end process;

我认为不使用inout也会更好，因为它并不总是适合合成，而是使用内部信号，存储out_lfsr值。

entity lfsr is

port(
    rst,clk,clk_en:in std_logic;
    out_lfsr: out std_logic_vector(31 downto 0);
    init_value: in std_logic_vector(31 downto 0)
);

end lfsr;

architecture Behavioral of lfsr is

signal s_out_lfsr : std_logic_vector(31 downto 0);
begin

process(clk)
begin
   if ( clk'event and clk ='1') then
      if (rst = '1') then
         s_out_lfsr <= init_value;
      elsif clk_en='1' then 
         s_out_lfsr(31 downto 1) <= s_out_lfsr(30 downto 0) ;
         s_out_lfsr(0) <= not(s_out_lfsr(31) XOR s_out_lfsr(21) XOR s_out_lfsr(0)); 
      end if;
   end if;
end process; 

out_lfsr <= s_out_lfsr;

end Behavioral;

我并不完全确定，因为您的代码是在编码示例中。