Question

我正在制作一个并行输出，并行输出寄存器，异步清除并与下降沿同步，我做了双稳态，我已经为寄存器做了这个：

LIBRARY IEEE;
USE ieee.STD_LOGIC_1164.ALL;
ENTITY registro_PP IS
    GENERIC (num_bits : NATURAL);
    PORT (
        clock, clr : IN STD_LOGIC;
        ent_datos : IN STD_LOGIC_VECTOR((num_bits - 1)DOWNTO 0);
        sal_datos : OUT STD_LOGIC_VECTOR ((num_bits - 1)DOWNTO 0)
    );
END registro_PP;

ARCHITECTURE con_generate OF registro_PP IS
    COMPONENT biestable_D_con_Clr IS
        PORT (d, clock, clr : IN STD_LOGIC;
            q : OUT STD_LOGIC);
        END COMPONENT;
        SIGNAL conec : STD_LOGIC_VECTOR ((num_bits - 1)DOWNTO 0);
        SIGNAL salida : STD_LOGIC_VECTOR ((num_bits - 1)DOWNTO 0);
    BEGIN
        B : FOR I IN 0 TO num_bits - 1 GENERATE
            U : biestable_D_con_Clr
            PORT MAP(
                d => conec (i), clock => clock, clr => clr, q => 
                salida (i)
            );
        END GENERATE;
END con_generate;

我也接受了这个测试：

LIBRARY IEEE;
USE ieee.STD_LOGIC_1164.ALL;
ENTITY regPPtest IS
END regPPtest;
ARCHITECTURE regPPArch OF regPPtest IS
    COMPONENT registro_PP IS
        GENERIC (num_bits : NATURAL);
        PORT (
            clock, clr : IN STD_LOGIC;
            ent_datos : IN STD_LOGIC_VECTOR((num_bits - 1)DOWNTO 0);
            sal_datos : OUT STD_LOGIC_VECTOR ((num_bits - 1)DOWNTO 0)
        );
    END COMPONENT;
    SIGNAL entrada : STD_LOGIC_VECTOR((5 - 1)DOWNTO 0);
    SIGNAL salida : STD_LOGIC_VECTOR((5 - 1)DOWNTO 0);
    SIGNAL poner_cero : STD_LOGIC;
    SIGNAL reloj : STD_LOGIC := '0';
    CONSTANT periodo : TIME := 10 ns;
    FOR U1 : registro_PP USE ENTITY WORK.registro_pp (con_generate);
    BEGIN
        U1 : registro_PP
            GENERIC MAP(5)
            PORT MAP
            (clock => reloj, clr => poner_cero, ent_datos => entrada, sal_datos => salida);
            reloj <= NOT reloj AFTER periodo/2;
            entrada <= "00000", "00001" AFTER 8 NS, "00011" AFTER 18 NS, "00111" AFTER 26
                NS, "01111" AFTER 36 NS, "11111" AFTER 46 NS, 
                "11110" AFTER 56 ns, "11100" AFTER 66 ns, "11000" AFTER 87 ns;
                poner_cero <= '1', '1' AFTER 11 NS, '0' AFTER 47 NS, '0' AFTER 58 NS;
END regPPArch;

当我尝试模拟它时出现问题，我收到了这个警告

 # ** Warning: (vsim-8683) Uninitialized out port /regpptest/U1/sal_datos(4) 
 has no driver.
 # 
 # This port will contribute value (U) to the signal network.
 # ** Warning: (vsim-8683) Uninitialized out port /regpptest/U1/sal_datos(3) 
 has no driver.
 # 
 # This port will contribute value (U) to the signal network.
 # ** Warning: (vsim-8683) Uninitialized out port /regpptest/U1/sal_datos(2) 
 has no driver.
 # 
 # This port will contribute value (U) to the signal network.
 # ** Warning: (vsim-8683) Uninitialized out port /regpptest/U1/sal_datos(1) 
 has no driver.
 # 
 # This port will contribute value (U) to the signal network.
 # ** Warning: (vsim-8683) Uninitialized out port /regpptest/U1/sal_datos(0) 
 has no driver.
 # 
 # This port will contribute value (U) to the signal network.

我一直在寻找代码中的错误几个小时，试图改变一些东西，但我无法解决它，所以我希望有人可以帮助我。

Answer 1

据我所知，你没有将任何东西连接到sal_datos，这就是为什么它没有被初始化。实际上，ent_datos（实体内部）的情况也是如此。

Answer 2

这看起来很简单。您定义了conec和salida，但从未附加任何内容。只需添加声明：

conec <= ent_datos;
sal_datos <= salida;

实体registro_PP中的

。

VHDL未初始化的端口没有驱动程序

2 个答案: