Question

我正在使用DE0 FPGA制作简单的游戏。我在VHDL中遇到VGA问题。我试图通过VGA在屏幕上显示一个简单的矩形，但没有出现。这是我的代码。请帮我找到问题。

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY vga IS
PORT( 
CLOCK_50:IN std_logic;
VGA_HS,VGA_VS:OUT std_logic;
VGA_R,VGA_G,VGA_B:OUT std_logic_vector(3 downto 0));
END vga;
ARCHITECTURE main OF vga IS 
SIGNAL VGCLK :std_logic:='0';
COMPONENT scyn IS 
PORT( 
 clk : IN std_logic;
 Hsync,Vsync:OUT std_logic;
 R,G,B:OUT std_logic_vector(3 downto 0));
 END COMPONENT; 

 COMPONENT freq_div1 IS 
PORT ( clkin : IN std_logic ;
       clkout :OUT std_logic ) ; 

END COMPONENT freq_div1  ;
Begin
 freq : freq_div1 port map (CLOCK_50 , VGCLK ) ;
 sync1: scyn      PORT MAP (VGCLK,VGA_HS,VGA_VS,VGA_R,VGA_G,VGA_B);

END main;

分频器从套件的50 MHZ获得25 MHZ

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;    
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY freq_div1 IS 
PORT ( clkin : IN std_logic ;
       clkout :OUT std_logic ) ; 
         END freq_div1  ;

ARCHITECTURE A OF freq_div1 IS 
BEGIN 
PROCESS (clkin )

   variable count  : std_logic_vector (1 downto 0) := "00";
begin
if (rising_edge (clkin )) THEN 
          count := count+1 ;
        end if;
        clkout <= count(0) ;
    end process ;
     END A ;

640x480分辨率

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE WORK.my.ALL;
ENTITY scyn IS 
PORT( 
 clk : IN std_logic;
 Hsync,Vsync:OUT std_logic;
 R,G,B:OUT std_logic_vector(3 downto 0));
 END scyn;
 ARCHITECTURE main OF scyn IS 
 SIGNAL RGB:std_logic_vector(3 downto 0);
 SIGNAL DRAW :std_logic;
 SIGNAL SQ_X1, SQ_Y1:INTEGER RANGE 0 TO 800:=0;
 SIGNAL Hpos: INTEGER RANGE 0 TO 800:=0;
 SIGNAL Vpos: INTEGER RANGE 0 TO 525:=0;
 BEGIN
 SQ_X1<= 480;
 SQ_Y1<=285;
PROCESS (clk)
BEGIN 
 IF (clk'EVENT AND  clk ='1') THEN 
 IF (DRAW='1') THEN 
 R<=RGB;
 G<=RGB;
 B<=RGB;
 ELSE 
 R<=(OTHERS =>'0');
 G<=(OTHERS =>'0');
 B<=(OTHERS =>'0');
 IF ( Hpos <800) THEN 
 Hpos<=Hpos+1;
 ELSE
 Hpos<=0;
 IF ( Vpos <525) THEN 
 Vpos<=Vpos+1;
 ELSE
 Vpos<=0;
 END IF; 
 END IF; 
 IF (Hpos >=16 AND Hpos<112) THEN 
 Hsync<='0';
 ELSE 
 Hsync<='1';
 END IF; 

  IF (Vpos>10 AND Hpos<12) THEN 
 Vsync<='0';
 ELSE 
 Vsync<='1';
 END IF; 
 IF ((Hpos>0 AND Hpos<160) OR (Vpos>0 AND Vpos<45)) THEN 
 R<=(OTHERS =>'0');
 G<=(OTHERS =>'0');
 B<=(OTHERS =>'0');
 END IF; 
 END IF; 
 END IF; 
 END PROCESS; 
 END main;

绘制regtangle

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
PACKAGE my IS 
PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos:IN INTEGER; SIGNAL RGB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DRAW :OUT std_logic);  
END my;
PACKAGE BODY my IS 
PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos:IN INTEGER; SIGNAL RGB :OUT STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL DRAW :OUT std_logic )  IS
BEGIN 
IF (Xcur>Xpos AND Xcur<(Xpos+100)  AND  Ycur>Ypos  AND Ycur <(Ypos+100))
THEN 
RGB <="1111";
DRAW<='1';
ELSE 
DRAW<='0';
END IF; 
END SQ; 
END my;

使用DE0的VHDL VGA

0 个答案: