如何在VHDL中对确定显示器的水平和垂直坐标的模块进行编码

时间:2019-05-27 09:40:20

标签: vhdl vga

我正在使用vhdl为学校项目编码游戏,我需要编写一个模块来 确定屏幕的水平和垂直位置,我写了一个,但是它不能正确工作。我认为问题出在边界数上,但我不知道如何纠正它,您能帮忙吗?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Sync_To_Row_And_Column is
port(
    vga_clk : in std_logic;
    global_reset : in std_logic;
    hdisp : in std_logic;
    vdisp : in std_logic;
    hpos : out integer;
    vpos : out integer
);
end Sync_To_Row_And_Column;

architecture Behavioral of Sync_To_Row_And_Column is

begin
    process(vga_clk,hdisp,vdisp,global_reset) 
        variable hpos_temp : integer range 1 to 640 := 1 ;
        variable vpos_temp : integer range 1 to 480 := 1 ;
        variable counter : integer := 0;
    begin 
        if(global_reset = '1') then
            hpos_temp := 1;
            vpos_temp := 1;
            counter := 0;
        elsif (vga_clk'event and vga_clk='1') then
            if (vdisp ='1' and hdisp = '1') then 
                counter := counter + 1;
                if(counter >= 639)then
                    vpos_temp := vpos_temp + 1;
                    counter := 0;
                end if;
                hpos_temp := hpos_temp + 1;
            end if; 
        end if;
        hpos <= hpos_temp;
        vpos <= vpos_temp;
    end process;
end Behavioral;

0 个答案:

没有答案