Question

我试图在Verilog中实现两个移位寄存器，用于根据两个输入信号之间的时间差返回输出值。

每0.5ms移位寄存器向右移位，第0个索引用输入信号的当前状态替换。如果输入之间的时间差小于或等于10ms，我想要将输出增加/减少2.如果它在10ms到40ms之间，我想要将输出增加/减少1.

我试图尽可能多地评论下面的代码来解释我目前的方法。我被告知要使用数字逻辑来实现这一点，而不是使用简单的计数器和case语句来确定时差。由于某种未知原因，移位寄存器中的值未正确“移位”。经过故障排除后，我发现只有resORMSB2在一个阶段处于高电平状态（将每个OR输出的输出连接到LED以确定每个状态）这没有任何意义。

任何帮助将不胜感激，如果我的描述不清楚，我道歉 - 我最近开始与Verilog合作并且我刚学习。

input signalOne; // Input signal 1
input signalTwo; // Input signal 2
input clk; // 50Mhz clock

output reg [15:0] outNumber = 0; // output number

reg [160:0] inputShiftReg = 161'd0; // Shift register containing the input(s) of signal 2
reg [80:0] outputShiftReg = 81'd0; // Shift register containing the input(s) of signal 1
reg [27:0] clkCount = 28'd0; // 28Bit counter to store the current clock count [0-268435456]

// Result of the 'first level' OR gates
reg resORMSB1 = 0; // Result of first MSB OR gate 
reg resORMSB2 = 0; // Result of second MSB OR Gate
reg resORLSB1 = 0; // Result of first LSB OR gate
reg resORLSB2 = 0; // Result of second LSB OR gate

// Result of the 'second level' AND gates
reg resANDMSB1 = 0; // Result of first MSB AND gate 
reg resANDMSB2 = 0; // Result of second MSB AND gate 
reg resANDLSB1 = 0; // Result of first LSB AND gate 
reg resANDLSB2 = 0; // Result of second LSB AND gate 

always @ (posedge clk) // On the rising edge of the 50MHz clock
    begin
        // Every 0.5 [ms] OR [400 Hz]
        clkCount <= clkCount + 1;
        if (clkCount == 28'd62500)   
            begin
                clkCount <= 0;
                // Update the input shift register
                inputShiftReg <= inputShiftReg >> 1; // Bitshift the input shift register right by 1Bit
                inputShiftReg[0] = signalOne; // Assign signalOne to inputShiftReg[0]
                // Update the output shift register
                outputShiftReg <= outputShiftReg >> 1; // Bitshift the output shift register right by 1Bit
                outputShiftReg[0] = signalTwo; // Assign signalTwo to outputShiftReg[0]
                // Determine the outputs of the 'first level' OR gates
                resORMSB1 <= |inputShiftReg[79:60]; // [-20 to -1]
                resORMSB2 <= |inputShiftReg[79:0];  // [-80 to -1]
                resORLSB1 <= |inputShiftReg[100:81]; // [1 to 20  ]
                resORLSB2 <= |inputShiftReg[160:81]; // [1 to 80  ]
                // Determine the outputs of the 'second level' AND gates
                resANDMSB1 <= resORMSB1 & outputShiftReg[80]; 
                resANDMSB2 <= resORMSB2 & outputShiftReg[80];
                resANDLSB1 <= resORLSB1 & outputShiftReg[80];
                resANDLSB2 <= resORLSB2 & outputShiftReg[80];
                // Determine the output number change       
                outNumber <= outNumber + resANDLSB1 + resANDLSB2 - resANDMSB1 - resANDMSB2;
            end
    end

endmodule

Verilog中的移位寄存器实现

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