Question

我试图使用自己创建的功能（这是我第一次尝试这样做，所以我可能在那里做错了。）

当我尝试编译时，我收到以下错误消息：错误（13815）：Averageador.vhd（38）中的VHDL限定表达式错误：限定表达式中指定的除法类型必须匹配由上下文表达的无符号类型< / p>

Divide是我的功能名称。此函数将任意16位无符号值除以未知无符号值，并将结果作为固定点32位无符号值给出，其中16位位于该点的每一侧。这是代码：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

package propios is

 --function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios;   --end of package.

package body propios is  --start of package body
--definition of function
function  divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+7 downto 0):= (others => '0');
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(31 downto 0):= (others => '0');
begin
a_int(a'length+7 downto 16):=a;
for i in a'length+7 downto 0 loop
    r(b'length downto 1):=r(b'length-1 downto 0);
    r(0) := a_int(i);
    if (r>=q) then
        r:=r-b_int;
        q(i):='1';
    end if;
end loop;
return q;
end divide;
--end function
end propios;  --end of the package body

我返回q，这是一个32位无符号。

这是我使用该函数并提示错误消息的代码：

   library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.propios.all;

ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.

END test;
Architecture simple of test is
signal a:unsigned(15 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(31 downto 0);
begin


process 
begin
a<="1100100110100111";
b<="00000000000010";
c<= divide(a,b);


end process;


end simple;

有什么建议吗？谢谢

Answer 1

问题是由于软件包上的软件包std_logic_arith和测试中的numeric_std引起的（如user1155120所说）。因此，即使两者都被称为无符号，它们也彼此不兼容。

这两个代码都包含其他错误，这些错误也已更正但与第一个错误无关。

这个包含一个函数，用于在昏迷后将2个无符号数除以16位：

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package propios is

 --function declaration.
function divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED;
end propios;   --end of package.

package body propios is  --start of package body
--definition of function
function  divide (a : UNSIGNED; b: UNSIGNED) return UNSIGNED is
variable a_int : unsigned(a'length+15 downto 0):= (others => '0');--Length is 16 bit longer than a
variable b_int : unsigned(b'length-1 downto 0):=b;
variable r : unsigned(b'length downto 0):= (others => '0');
variable q : unsigned(a'length+15 downto 0):= (others => '0');--Same length as a_int
variable i: natural;

begin
a_int(a'length+15 downto 16):=a;--the MSBits are "a" and the rest will be 0's
for i in a'length+15 downto 0 loop--division using a modified version of integer division (unsigned) with remainder as seen in:
--https://en.wikipedia.org/wiki/Division_algorithm
    r(b'length downto 1):=r(b'length-1 downto 0);
    r(0) := a_int(i);
    if (r>=b_int) then
        r:=r-b_int;
        q(i):='1';
    end if;
end loop;
return q;
end divide;
--end function
end propios;  --end of the package body

这是检查其功能的简单测试：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.propios.all;

ENTITY test IS --Con alimentación de datos posición a posición, no vector de golpe.

END test;
Architecture simple of test is
signal a:unsigned(23 downto 0);
signal b:unsigned(13 downto 0);
signal c: unsigned(39 downto 0);
begin


process 
begin
a<="000000001100100110100111";
b<="00000000010010";
wait for 200ps;
c<= divide (a , b);

wait;   
end process;


end simple;

要检查结果，请记住结果的最后16位位于固定点之后。

VHDL错误：限定表达式中指定的类型必须与上下文表达式隐含的类型匹配

1 个答案: