Question

我正在用VHDL编写一个基本的组合电路，它有一个带有两个输入a和b的AND门。该“t”的输出与否定输入“c”进行“或”运算。然后，此输出“s”为NAND，带有“a”，以给出最终输出“d”。

这是代码。

library ieee;
use ieee.std_logic_1164.all;
entity logicgate is
port(a,b,c: in std_logic;
d: out std_logic);
end logicgate;

architecture arch_logicgate of logicgate is
begin
signal s: std_logic;
signal t: std_logic;
t<= a and b;
s<= (not c) or t;
d<= a nand s;
end arch_logicgate;

文稿：

-- Compiling architecture arch_logicgate of logicgate
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s".
# 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC.
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting

我知道我错过了基础知识。请帮帮我。

Answer 1

第一条错误消息：

** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error

之所以出现是因为执行区域中存在声明。

在begin

之前将它们放在声明区域中

architecture arch_logicgate of logicgate is
   signal s: std_logic;
begin
   ...

键入错误中缀表达式VHDL

1 个答案: