Question

当我尝试编译此代码时，我不断收到错误消息：

line 13: Error, 'std_logic' is not a known type.

第13行是Clock : IN std_logic;实体中的ALU_tb。

我对此错误感到困惑，因为我的理解是所述错误的原因通常是缺少库/包。我几乎可以肯定我有适当的库和包。另外，std_logic类型的其他信号都没有出错。

如果有人能帮助我解决这个问题，我将非常感激。

-- VHDL Entity ALU.ALU_tb.symbol
--
-- Created:
--          by - ClarkG.UNKNOWN (COELABS15)
--          at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--


ENTITY ALU_tb IS
   PORT( 
      Clock   : IN     std_logic;
      Reset_N : IN     std_logic
   );

-- Declarations

END ALU_tb ;

--
-- VHDL Architecture ALU.ALU_tb.struct
--
-- Created:
--          by - ClarkG.UNKNOWN (COELABS15)
--          at - 19:58:20 09/ 8/2014
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2011.1 (Build 18)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY ALU;

ARCHITECTURE struct OF ALU_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL A        : std_logic_vector(31 DOWNTO 0);
   SIGNAL ALUOp    : std_logic_vector(3 DOWNTO 0);
   SIGNAL B        : std_logic_vector(31 DOWNTO 0);
   SIGNAL Overflow : std_logic;
   SIGNAL R        : std_logic_vector(31 DOWNTO 0);
   SIGNAL SHAMT    : std_logic_vector(4 DOWNTO 0);
   SIGNAL Zero     : std_logic;


   -- Component Declarations
   COMPONENT ALU
   PORT (
      A        : IN     std_logic_vector (31 DOWNTO 0);
      ALUOp    : IN     std_logic_vector (3 DOWNTO 0);
      B        : IN     std_logic_vector (31 DOWNTO 0);
      SHAMT    : IN     std_logic_vector (4 DOWNTO 0);
      Overflow : OUT    std_logic ;
      R        : OUT    std_logic_vector (31 DOWNTO 0);
      Zero     : OUT    std_logic 
   );
   END COMPONENT;
   COMPONENT ALU_tester
   PORT (
      A        : IN     std_logic_vector (31 DOWNTO 0);
      ALUOp    : IN     std_logic_vector (3 DOWNTO 0);
      B        : IN     std_logic_vector (31 DOWNTO 0);
      Clock    : IN     std_logic ;
      Overflow : IN     std_logic ;
      R        : IN     std_logic_vector (31 DOWNTO 0);
      Reset_N  : IN     std_logic ;
      SHAMT    : IN     std_logic_vector (4 DOWNTO 0);
      Zero     : IN     std_logic 
   );
   END COMPONENT;
   COMPONENT Test_transaction_generator
   PORT (
      Clock : IN     std_logic ;
      A     : OUT    std_logic_vector (31 DOWNTO 0);
      ALUOp : OUT    std_logic_vector (3 DOWNTO 0);
      B     : OUT    std_logic_vector (31 DOWNTO 0);
      SHAMT : OUT    std_logic_vector (4 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ALU USE ENTITY ALU.ALU;
   FOR ALL : ALU_tester USE ENTITY ALU.ALU_tester;
   FOR ALL : Test_transaction_generator USE ENTITY ALU.Test_transaction_generator;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : ALU
      PORT MAP (
         A        => A,
         ALUOp    => ALUOp,
         B        => B,
         SHAMT    => SHAMT,
         Overflow => Overflow,
         R        => R,
         Zero     => Zero
      );
   U_1 : ALU_tester
      PORT MAP (
         A        => A,
         ALUOp    => ALUOp,
         B        => B,
         Clock    => Clock,
         Overflow => Overflow,
         R        => R,
         Reset_N  => Reset_N,
         SHAMT    => SHAMT,
         Zero     => Zero
      );
   U_2 : Test_transaction_generator
      PORT MAP (
         Clock => Clock,
         A     => A,
         ALUOp => ALUOp,
         B     => B,
         SHAMT => SHAMT
      );

END struct;

Answer 1

由库子句和use子句组成的context子句应该在实体声明之前而不是在体系结构体之前移动。实体和体系结构形成一个公共声明区域，允许这些库和使用子句在两者之间生效，而不仅仅是体系结构，就像在您的代码中一样。

您似乎也没有在您显示的代码中使用包std_logic_arith。（该架构仅包含组件）。

Answer 2

在第13行，您尚未导入定义std_logic所需的ieee库，这就是您收到错误的原因。

在VHDL中键入错误

2 个答案: