Question

我在线找到了一个简单处理器的以下代码。我正在尝试使用hAMSter在VHDL AMS中添加一些模拟组件。但它正在生成错误：类型不匹配

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; 

entity program_counter is
port (
   clk, en_A, ld, inc, reset: in STD_LOGIC;
   aBus: out STD_LOGIC_VECTOR(15 downto 0);
   dBus: in STD_LOGIC_VECTOR(15 downto 0)
);
end program_counter;
architecture pcArch of program_counter is
signal pcReg : STD_LOGIC_VECTOR(15 downto 0);
begin
process(clk) begin
   if clk'event and clk = '1' then 
         if reset = '1' then
               pcReg <= x"0000";
         elsif ld = '1' then
               pcReg <= dBus;
         elsif inc = '1' then
       pcReg <= pcReg + x"0001";
         end if;
   end if;
end process;
aBus <= pcReg when en_A = '1' else "ZZZZZZZZZZZZZZZZ";
end pcArch;

特别是在线：

pcReg <= pcReg + x"0001";

错误是：

(ARCHITECTURE pcarch OF ENTITY program_counter) : Error : Type mismatch

请帮助修复。

Answer 1

因为看到你只做了一半的工作太令人沮丧了。（单独更改库当然不会修复它...）

library IEEE;
use IEEE.std_logic_1164.all;

entity program_counter is
    port (
        clk, en_A, ld, inc, reset: in STD_LOGIC;
        dBus: in STD_LOGIC_VECTOR(15 downto 0);
        aBus: out STD_LOGIC_VECTOR(15 downto 0)
    );
end entity;

architecture pcArch of program_counter is
    use ieee.numeric_std.all; 
    signal pcReg : unsigned(15 downto 0) := (others => '0');
begin
    process(clk) begin
        if rising_edge(clk) then 
            if reset = '1' then
                pcReg <= (others => '0');
            elsif ld = '1' then
                pcReg <= unsigned(dBus);
            elsif inc = '1' then
                pcReg <= pcReg + 1;
            end if;
        end if;
    end process;
    aBus <= std_logic_vector(pcReg) when en_A = '1' else (others => 'z');
end architecture;

请：下次做更好的搜索。这是非常常见/简单的代码，并且可以在整个网络上获得示例。

（ARCHITECTURE pcarch OF ENTITY program_counter）：错误：类型不匹配

1 个答案: