VHDL-SHIFT_RIGHT类型必须匹配std_logic_vector

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity compute is
    port(
        clk: in std_logic;
        sw: in std_logic_vector(1 downto 0);    
        count1: in std_logic_vector(17 downto 0):=X"30";
        count2: in std_logic_vector(17 downto 0):=X"30";
        result1: out integer range 0 to 15;
        result2: out integer range 0 to 15
        );
            end compute;

architecture behavioral of compute is
    signal signal1: std_logic_vector(17 downto 0):=X"30";
    signal signal2: std_logic_vector(17 downto 0):=X"30";
    signal signal3: std_logic_vector(17 downto 0):=X"30";
    signal signal4: std_logic_vector(17 downto 0):=X"30";
    signal count_temp1:  std_logic_vector(17 downto 0):=X"00";
    signal count_temp2:  std_logic_vector(17 downto 0):=X"00";
        begin
            process(clk,sw)
                begin
                    if (rising_edge(clk)) then
                        count_temp1<=count1;
                        count_temp2<=count2;
                        if (sw(0)='0') then
                            count_temp1<=x"03";
                            count_temp2<=x"03";
                            elsif (sw(1)='0') then
                                signal1<= (shift_right(unsigned(count1), 0)) xor (shift_right(unsigned(count1), 7)); 
                                signal2<= (shift_right(unsigned(count2), 0)) xor (shift_right(unsigned(count2), 7)); 
                                signal3<= signal1 and "1";
                                signal4<= signal2 and "1";
                                count1<= (shift_right((count1), 1)) or (shift_left((signal3), 17));
                                count2<= (shift_right((count2), 1)) or (shift_left((signal4), 17));
                                count_temp1<=count1(11 downto 4);
                                count_temp2<=count2(11 downto 4);
                                    end if;
                                        result1<=to_integer(unsigned(count_temp1));
                                        result2<=to_integer(unsigned(count_temp2));
                                            end if;
                                                end process;
                                                    end behavioral;    

我是VHDL的新手，但收到一条错误消息，无法纠正。我收到以下错误消息。错误消息：错误（10511）：compute.vhd（33）处的VHDL合格表达式错误：在合格表达式中指定的SHIFT_RIGHT类型必须与上下文隐含表示的std_logic_vector类型匹配