Question

我有一个包含以下3个文件的项目，我在CA文件中收到此错误：

Line 65: Type error near state_int ; current type std_logic_vector; expected type std_logic
ERROR:HDLCompiler:854 - "" Line 40: Unit  ignored due to previous errors.

CA FILE

SELECT TOP (100) PERCENT dbo.SorDetail.MLineShipDate
    , dbo.SorMaster.SalesOrder
    , dbo.SorDetail.SalesOrderLine
    , dbo.SorMaster.CustomerPoNumber
    , dbo.SorMaster.Customer
    ...
    , CASE 
        WHEN IntWhSales = 'Y'
            THEN OrderQtyCurrent
        ELSE OrderQtyOrig
    END                           AS [OrderQuantity]
FROM dbo.ShortOrderTrimQty
RIGHT OUTER JOIN dbo.SorMaster
...

CELL FILE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CA is

    port(clk,rst:in std_logic;
             state:out std_logic_vector(0 to 8)
            );

end CA;

architecture Behavioral of CA is

    Component cell
        port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );
    end component;

    Component cellm
        port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );
    end component;

    signal state_int:std_logic_vector(0 to 8);

begin


    state <= state_int; 
    U_cell0:cell

    port map(clk => clk,
                rst =>rst,
                L => '0',
                R => state_int,
                state => state_int(0)
                );


end Behavioral;

CELLM FILE

entity cell is

    port(L,R,clk,rst:in std_logic;
                 state:out std_logic
            );

end cell;

architecture Behavioral of cell is

signal state_pr,state_nx:std_logic;

begin

    state_nx <= ((not L) and R and state_pr) or (L and (not R));

    Process(clk,rst)
    Begin
        if rst = '0' then
            state_pr <= '0';    
        elsif rising_edge(clk) then
            state_pr <= state_nx;
        end if;
    end process;    

end Behavioral;

我做错了什么？

Answer 1

实际上你的设计有三个问题。评论中提到了前两个问题：

您正在尝试连接std_logic_vector信号 state_int 和std_logic端口 R 。显然，由于不匹配（单线和多线），这将无法正常工作
在下一行中，您还尝试连接std_logic_vector信号状态和std_logic端口 state_int（0）。
您的单元格实体中还有另一个问题。状态输出永远不会分配给任何内容。因此，单元实体将没有实际输出。您最终可能会收到编译器关于此的警告。

（vhdl）std_logic_vector值

1 个答案: