我对此Verilog代码有疑问。我的代码消耗了双重寄存器，我很困惑为什么？我想知道，我该如何优化它？我想可以使用case语句进行改进，但我不知道如何使用它。
input clk;
input [1:0] en;
reg [7:0] r16,r15,r14,r13,r12,r11,r10,r9,r8,r7,r6,r5,r4,r3,r2,r1;
wire [7:0] mux_state0_out,mux_state1_out,mux_state2_out,mux_state3_out;
always @(posedge clk) begin
if (en==2'b01) begin
r4 <= r4;
r3 <= r3;
r2 <= r2;
r1 <= r1;
r7 <= r8;
r6 <= r7;
r5 <= r6;
r8 <= r5;
r10 <= r12;
r9 <= r11;
r12 <= r10;
r11 <= r9;
r13 <= r16;
r16 <= r15;
r15 <= r14;
r14 <= r13;
end
else begin
r16 <= mux_state0_out;
r15 <= r16;
r14 <= r15;
r13 <= r14;
r12 <= mux_state1_out;
r11 <= r12;
r10 <= r11;
r9 <= r10;
r8 <= mux_state2_out;
r7 <= r8;
r6 <= r7;
r5 <= r6;
r4 <= mux_state3_out;
r3 <= r4;
r2 <= r3;
r1 <= r2;
end
end
endmodule