Question

我正在为简单的上下游戏制作Verilog代码。为此，我必须输入一个4位数的十进制数字。

module Updown(
    Reset, Clk,
    SEG_COM, SEG_DATA, // 4 digit binary number
    a,b,c,d,e,f,g, // u, d, O
    bta, btb, btc, btd, bte, btf, btg, bth, bti, btj
    );
     input Reset, Clk;
     input bta, btb, btc, btd, bte, btf, btg, bth, bti, btj;

     output a,b,c,d,e,f,g;
     output reg [3:0] SEG_COM;
     output reg [7:0] SEG_DATA;


     integer CNT_SCAN;
     integer CNT;

     reg [3:0] Num_in;
     reg [15:0] Num;
     reg bta1, btb1, btc1, btd1, bte1, btf1, btg1, bth1, bti1, btj1; // one shot control
     wire bt1, bt2, bt3, bt4, bt5, bt6, bt7, bt8, bt9, bt0;

     always @(posedge Clk or negedge Reset)
     begin
      if (~Reset)
      begin
      bta1 = 0;
      btb1 = 0;
      btc1 = 0;
      btd1 = 0;
      bte1 = 0;
      btf1 = 0;
      btg1 = 0;
      bth1 = 0;
      bti1 = 0;
      btj1 = 0;
      end
      else
       begin
        bta1 = bta;
       btb1 = btb;
       btc1 = btc;
       btd1 = btd;
       bte1 = bte;
       btf1 = btf;
       btg1 = btg;
       bth1 = bth;
       bti1 = bti;
       btj1 = btj;
        end
     end

     assign bt1 = bta & ~bta1;
     assign bt2 = btb & ~btb1;
     assign bt3 = btc & ~btc1;
     assign bt4 = btd & ~btd1;
     assign bt5 = bte & ~bte1;
     assign bt6 = btf & ~btf1;
     assign bt7 = btg & ~btg1;
     assign bt8 = bth & ~bth1;
     assign bt9 = bti & ~bti1;
     assign bt0 = btj & ~btj1;

     always @(posedge Clk)
     begin
     if (bt1)
     Num_in = 1;
     else if (bt2)
     Num_in = 2;
     else if (bt3)
     Num_in = 3;
     else if (bt4)
     Num_in = 4;
     else if (bt5)
     Num_in = 5;
     else if (bt6)
     Num_in = 6;
     else if (bt7)
     Num_in = 7;
     else if (bt8)
     Num_in = 8;
     else if (bt9)
     Num_in = 9;
     else if (bt0)
     Num_in = 0;
     end


     always @(posedge Clk or negedge Reset)
     begin
     if (~Reset)
     Num = 4'b0000;
     else
     begin
      Num[3:0] = Num[7:4];
      Num[7:4] = Num[11:8];
      Num[11:8] = Num[15:12];
      Num[15:12] = Num_in [3:0];
     end
     end

     always @(posedge Clk or negedge Reset)
     begin
     if (~Reset)
     CNT_SCAN = 0;
     else
      begin
      if (CNT_SCAN >=3)
      CNT_SCAN = 0;
      else
      CNT_SCAN = CNT_SCAN + 1;
      end
     end

     always @(posedge Clk or negedge Reset)
     begin
     if (~Reset)
     begin
     SEG_COM = 4'hF;
     SEG_DATA = 8'h00;
     end
     else
      begin
      case (CNT_SCAN)
      0 : begin
      SEG_COM = 4'h7;
      case (Num[3:0])
      0 : SEG_DATA = 8'b11111100;
      1 : SEG_DATA = 8'b01100000;
      2 : SEG_DATA = 8'b11011010;
      3 : SEG_DATA = 8'b11110010;
      4 : SEG_DATA = 8'b01100110;
      5 : SEG_DATA = 8'b10110110;
      6 : SEG_DATA = 8'b10111110;
      7 : SEG_DATA = 8'b11100100;
      8 : SEG_DATA = 8'b11111110;
      9 : SEG_DATA = 8'b11110110;
      default : SEG_DATA = 8'h00;
      endcase
      end
      1 : begin
      SEG_COM = 8'hB;
      case (Num[7:4])
      0 : SEG_DATA = 8'b11111100;
      1 : SEG_DATA = 8'b01100000;
      2 : SEG_DATA = 8'b11011010;
      3 : SEG_DATA = 8'b11110010;
      4 : SEG_DATA = 8'b01100110;
      5 : SEG_DATA = 8'b10110110;
      6 : SEG_DATA = 8'b10111110;
      7 : SEG_DATA = 8'b11100100;
      8 : SEG_DATA = 8'b11111110;
      9 : SEG_DATA = 8'b11110110;
      default : SEG_DATA = 8'h00;
      endcase
      end
      2 : begin
      SEG_COM = 8'hD;
      case (Num[11:8])
      0 : SEG_DATA = 8'b11111100;
      1 : SEG_DATA = 8'b01100000;
      2 : SEG_DATA = 8'b11011010;
      3 : SEG_DATA = 8'b11110010;
      4 : SEG_DATA = 8'b01100110;
      5 : SEG_DATA = 8'b10110110;
      6 : SEG_DATA = 8'b10111110;
      7 : SEG_DATA = 8'b11100100;
      8 : SEG_DATA = 8'b11111110;
      9 : SEG_DATA = 8'b11110110;
      default : SEG_DATA = 8'h00;
      endcase
      end
      3 : begin
      SEG_COM = 8'hE;
      case (Num[15:12])
      0 : SEG_DATA = 8'b11111100;
      1 : SEG_DATA = 8'b01100000;
      2 : SEG_DATA = 8'b11011010;
      3 : SEG_DATA = 8'b11110010;
      4 : SEG_DATA = 8'b01100110;
      5 : SEG_DATA = 8'b10110110;
      6 : SEG_DATA = 8'b10111110;
      7 : SEG_DATA = 8'b11100100;
      8 : SEG_DATA = 8'b11111110;
      9 : SEG_DATA = 8'b11110110;
      default : SEG_DATA = 8'h00;
      endcase
      end
      default : begin
      SEG_COM = 8'hFF;
      SEG_DATA = 8'h00;
      end
      endcase
      end
      end



endmodule

这不是最终版本，请立即制作。问题是当我按下一个按钮时，所有数字都是相同的。我想将其作为串行输入，例如当我按9321时，那么7段显示器应该显示9321，但现在它像9999、3333、2222、1111一样工作。感谢您的帮助。

Answer 1

我猜时钟运行得如此之快，以至于当您按下某个按钮时，它会更新周期0中的最低有效位，然后更新周期1中的下一个，依此类推，以此类推，以至于它们都结束了具有相同的值。您需要添加逻辑以仅在“在此循环中按下一个按钮但在上一个循环中未按下某个按钮”时才更新一位数字。

Answer 2

Num_in仅在按下按钮时更新。但是Num的内容降级并将其自身与Num_in连接。 Num也应该每按一次更新一次。您可以在按下按钮后添加一个翻牌以声明一个周期，也可以取消对Num_in的需求：

always @(posedge Clk or negedge Reset)
begin
  if (~Reset)
    Num <= 4'b0000;
  else if (bt1)
    Num[15:0] <= {4'd1, Num[15:4]};
  else if (bt2)
    Num[15:0] <= {4'd2, Num[15:4]};
  else if (bt3)
    Num[15:0] <= {4'd3, Num[15:4]};
  else if (bt4)
    Num[15:0] <= {4'd4, Num[15:4]};
  else if (bt5)
    Num[15:0] <= {4'd5, Num[15:4]};
  else if (bt6)
    Num[15:0] <= {4'd6, Num[15:4]};
  else if (bt7)
    Num[15:0] <= {4'd7, Num[15:4]};
  else if (bt8)
    Num[15:0] <= {4'd8, Num[15:4]};
  else if (bt9)
    Num[15:0] <= {4'd9, Num[15:4]};
  else if (bt0)
    Num[15:0] <= {4'd0, Num[15:4]};
end

仅供参考，同步逻辑应分配有非阻塞分配（<=）。这样做可以防止在仿真期间在Verilog调度程序中出现潜在的竞争条件（综合并不重要，但可能会发出警告）。

如何在Verilog中输入串行BCD代码

2 个答案: