这是我上课的任务。我们的任务是设计一个提供基本秒表功能的VHDL组件。您的设计应从零开始，并且能够在最右边的7段显示器上计数最多20个（其他两个显示器应为空白，除非如下所述）。按下中央按钮会使计数开始和停止。向下按钮将计数器重置为00.如果计数达到20，则板上的16个LED将创建复杂的胜利模式。
如何在两个不同的7segs上同时显示不同数字上的两个数字。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity lab_3 is
Port (
-------------led output-------------------------------------
led: out std_logic_vector(15 downto 0);
-------------button inputs----------------------------------
btnc: in std_logic;
btnd: in std_logic;
-----------7 seg outpus--------------------------------------------
seg: out std_logic_vector(6 downto 0); --MSB=a: LSB=g
-------------7 seg enables----------------------------------------
an: out std_logic_vector(3 downto 0)
);
end lab_3;
architecture Behavioral of lab_3 is
------decimal seven segment display--------------------------CONSTANTS
constant ZERO_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ONE_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWO_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THREE_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOUR_7SEG: std_logic_vector(6 downto 0) := "0011001";
constant FIVE_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIX_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHT_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINE_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TEN_7SEG: std_logic_vector(6 downto 0) := "1000000";
constant ELEVEN_7SEG: std_logic_vector(6 downto 0) := "1111001";
constant TWELVE_7SEG: std_logic_vector(6 downto 0) := "0100100";
constant THIRTEEN_7SEG: std_logic_vector(6 downto 0) := "0110000";
constant FOURTEEN_7SEG: std_logic_vector(6 downto 0) := "0110001";
constant FIFTEEN_7SEG: std_logic_vector(6 downto 0) := "0010010";
constant SIXTEEN_7SEG: std_logic_vector(6 downto 0) := "0000010";
constant SEVENTEEN_7SEG: std_logic_vector(6 downto 0) := "1111000";
constant EIGHTEEN_7SEG: std_logic_vector(6 downto 0) := "0000000";
constant NINETEEN_7SEG: std_logic_vector(6 downto 0) := "0010000";
constant TWENTY_7SEG: std_logic_vector(6 downto 0) := "1111001";
-------------------led dance-------------------------------------- ` constant step_one: std_logic_vector(15 downto 0):="0000000000000001";`
constant step_two: std_logic_vector(15 downto 0):="0000000000000010";
constant step_three: std_logic_vector(15 downto 0):="0000000000000100";
constant step_four: std_logic_vector(15 downto 0):="0000000000001000";
constant step_five: std_logic_vector(15 downto 0):="0000000000010000";
constant step_six: std_logic_vector(15 downto 0) :="0000000000100000";
constant step_seven: std_logic_vector(15 downto 0) :="0000000001000000";
constant step_eight: std_logic_vector(15 downto 0) :="0000000010000000";
constant step_nine: std_logic_vector(15 downto 0) :="0000000100000000";
constant step_ten: std_logic_vector(15 downto 0) :="0000001000000000";
constant step_eleven: std_logic_vector(15 downto 0):="0000010000000000";
constant step_twelve: std_logic_vector(15 downto 0):="0000100000000000";
constant step_thirteen: std_logic_vector(15 downto 0):="0001000000000000";
constant step_fourteen: std_logic_vector(15 downto 0) :="0010000000000000";
constant step_fifteen: std_logic_vector(15 downto 0) :="0100000000000000";
constant step_sixteen: std_logic_vector(15 downto 0):="1000000000000000";
---------------------active constants-----------------------------------
constant active: std_logic :='1';
constant inactive: std_logic :='0';
constant ACTIVE_RESET: std_logic := '0';
constant TERMINAL_VALUE: integer := 50000000;
-------------------internal connections-------------------------SIGNALS
signal Clock: std_logic;
signal Count: unsigned(7 downto 0);
signal DividedClock: std_logic;
signal Digit0: std_logic_vector(6 downto 0);
signal Digit1: std_logic_vector(6 downto 0);
signal DigitSelect: std_logic;
signal led_dance: std_logic_vector( 15 downto 0);
-----------------clock divider----------------------------
begin
process(Clock)
variable counter: integer range 0 to TERMINAL_VALUE;
begin
if (btnD=ACTIVE_RESET) then
counter := 0;
elsif (rising_edge(Clock)) then
counter := counter + 1;
if (counter = TERMINAL_VALUE) then
counter := 0;
DividedClock <= not DividedClock;
end if;
end if;
end process;
--------------------------counter-----------------------------
process(Clock)
begin
if (btnD=active) then
count <= "00000000";
elsif (rising_edge(Clock)) then
count <= count + 1;
end if;
end process;
-------------------BCD to 7seg--------------------------------
with count select
Digit0 <= ZERO_7SEG when "0000000",
ONE_7SEG when "0000001",
TWO_7SEG when "0000010",
THREE_7SEG when "0000011",
FOUR_7SEG when "0000100",
FIVE_7SEG when "0000101",
SIX_7SEG when "0000110",
SEVEN_7SEG when "0000111",
EIGHT_7SEG when "0001000",
NINE_7SEG when "0001001",
TEN_7SEG when "0001010",
ELEVEN_7SEG when "0001011",
TWELVE_7SEG when "0001100",
THIRTEEN_7SEG when "0001101",
FOURTEEN_7SEG when "0001110",
FIFTEEN_7SEG when "0001111",
SIXTEEN_7SEG when "0010000",
SEVENTEEN_7SEG when "0010001",
EIGHTEEN_7SEG when "0010010",
NINETEEN_7SEG when "0010011",
TWENTY_7SEG when others;
with count select
Digit1 <= ZERO_7SEG when "0000000",
ZERO_7SEG when "0000001",
ZERO_7SEG when "0000010",
ZERO_7SEG when "0000011",
ZERO_7SEG when "0000100",
ZERO_7SEG when "0000101",
ZERO_7SEG when "0000110",
ZERO_7SEG when "0000111",
ZERO_7SEG when "0001000",
ZERO_7SEG when "0001001",
TWO_7SEG when "0010100",
ONE_7SEG when others;
end Behavioral;
答案 0 :(得分：1)
我想您需要将Digit0或Digit1信号连接到seg输出端口。
根据我对这些显示器的经验，我假设所有四位数字都将显示由seg编码的模式。为了显示每个数字的不同模式，我们的想法是使用an输出快速打开和关闭各个数字，这样在切换{{1}时，在任何给定时刻只能打开其中一个数字。同时在seg和Digit0之间。
如果切换速度足够快，那么它就不会显而易见了。
答案 1 :(得分：0)
vhdl.us上有几个设计示例，包括SSD。