映射端口时Vivado输入/输出标准违规

Question

我正在编写一个vhdl模块，该模块将在Artix-7 Basys 3 FPGA板上实现。我的设计成功运行了综合和实现，但是当我运行写比特流时，我收到了这个错误：

  

[DRC 23-20]规则违规（NSTD-1）未指定的I / O标准 - 29个逻辑端口中的1个使用I / O标准（IOSTANDARD）值'DEFAULT'，而不是用户指定的特定值。这可能会导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。要更正此违规，请指定所有I / O标准。除非所有逻辑端口都定义了用户指定的I / O标准值，否则此设计将无法生成比特流。要允许使用未指定的I / O标准值创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。问题端口：segt [7]。

如您所见，它将segt列为问题端口。对于7段显示，我将其从“seg”重命名为“segt”，这是它的默认名称，但这并不能防止错误发生。这很奇怪，因为我在使用开关的默认名称“sw”和模块中的按钮“btnC”时遇到了这个错误。我在master.xdc文件中将“sw”重命名为“sw1”，将“btnC”重命名为“btnC1”，并且我停止获取这些特定端口的错误。任何帮助将不胜感激。

这是主要模块：

entity timer_test is
    port(
    clk: in std_logic;
    btnC1: in std_logic;
    an: out std_logic_vector(3 downto 0);
    segt: out std_logic_vector(7 downto 0);
    led: out std_logic_vector(15 downto 0);
    sw1: in std_logic_vector(15 downto 0)
    );
end timer_test;

architecture arch of timer_test is
    signal d3,d2, d1, d0: std_logic_vector(3 downto 0);
    signal one_sec: std_logic;
begin
    disp_unit: entity work.disp_hex_mux
      port map(
         clk=>clk, reset=>'0',
         hex3=>d3, hex2=>d2, hex1=>d1, hex0=>d0,
         dp_in=>"1101", an=>an, sseg=>segt);

    divider_unit: entity work.clock_divider
        port map(
            clk=>clk,
            start=>'1',
            onesec=>one_sec);

    counter_unit: entity work.count_down_timer
        port map(
            min_in(7 downto 0)=>sw1(15 downto 8),
            sec_in(7 downto 0)=>sw1(7 downto 0),
            clk=>clk,
            one_sec=>one_sec,
            reset=>btnC1,
            d3=>d3 ,d2 =>d2, d1=>d1, d0=>d0,
            led=>led);
end arch;

Master.xdc的相关部分：

## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]                         
    set_property IOSTANDARD LVCMOS33 [get_ports clk]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

## Switches
set_property PACKAGE_PIN V17 [get_ports {sw1[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw1[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw1[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw1[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw1[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw1[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw1[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw1[7]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw1[8]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw1[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw1[10]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw1[11]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw1[12]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw1[13]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw1[14]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw1[15]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {sw1[15]}]


## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]                   
    set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]


#7 segment display
set_property PACKAGE_PIN W7 [get_ports {segt[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[6]}]
set_property PACKAGE_PIN W6 [get_ports {segt[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[5]}]
set_property PACKAGE_PIN U8 [get_ports {segt[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[4]}]
set_property PACKAGE_PIN V8 [get_ports {segt[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[3]}]
set_property PACKAGE_PIN U5 [get_ports {segt[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[2]}]
set_property PACKAGE_PIN V5 [get_ports {segt[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[1]}]
set_property PACKAGE_PIN U7 [get_ports {segt[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {segt[0]}]

set_property PACKAGE_PIN V7 [get_ports dp]                          
    set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]                 
    set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC1]                      
    set_property IOSTANDARD LVCMOS33 [get_ports btnC1]

如何修复这些规则违规行为？

Answer 1

错误消息明确指出29个端口中只有1个受到影响，因此告诉我们我们只是在找一个有问题的引脚。错误消息的结尾指定WHERE。您对segt[7]的声明如下：

segt

请记住，在VHDL中，segt: out std_logic_vector(7 downto 0); 包含。这意味着downto有8个元素。

现在查看您的约束文件：没有为segt指定IO标准。您只包含segt[7]到segt[6]，但这些都不包含在您的错误中。只需添加segt[0]的IO标准规范：

segt[7]