VHDL - BCD到二进制输入缓冲区 - 显示结果的问题

时间:2017-01-29 00:34:24

标签: binary buffer vhdl state bcd

我正在使用Vivado 2014.2将BCD的VHDL代码写入可用于计算器或组合锁的二进制输入缓冲区。

我的方法很简单。做x * 10它与x(2 + 8)= x * 2 + x * 8相同。

x * 2 = 1左移(2 ^ 1 = 2)

x * 8 =左移3(2 ^ 3 = 8)

在添加输入之前移位并添加输出缓冲区(tempC)。这样做是为了从null开始,这样输入的第一个数字就不会出现,再乘以10。

我的代码在artix 7 fpga上编译并运行,但是我遇到了确保输出缓冲区(tempC)正常工作的问题。它拒绝输出任何数据,但我不确定原因。

我可能会错误地添加这些值,但我不这么认为。也许我正在使用错误的数据类型?

非常感谢任何帮助。

-- Engineer: greatgamer34
-- 
-- Create Date: 01/25/2017 04:57:02 PM
-- Design Name: 
-- Module Name: buff - Behavioral


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity buff is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input
       Clock : in STD_LOGIC;
       Reset : in STD_LOGIC;
       Output : out STD_LOGIC_VECTOR (15 downto 0);
       aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output             for current state.
end buff;

architecture Behavioral of buff is
type states is (state0, state1, state2, state3);
signal currentstate, nextstate: states;
signal tempA: STD_LOGIC_VECTOR (15 downto 0);---used to store 'Data' for addition.
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data').
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register.
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's.
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data')
begin
Process(Reset,clock)
Begin
if(Reset = '1') then
    tempC <= "0000000000000000"; --clear tempC
    tempA <= "0000000000000000"; --clear tempA
    currentstate <= state0; -------reset state to 0
elsif(clock'event and clock = '1') then  
     output <= (tempD);--dispaly the output of the buffer
      currentstate<=nextstate;  -- advance states   
end if;

end process;

process(currentstate)
begin
case currentstate is

when state0 =>
   tempA(3 downto 0) <= Data; -- load in 4 bit data intoi 16 bit register
   tempD <= (tempA); --output the input data(used for debugging)
    nextstate <= state1;
    aout <= not "1111110"; -- output on the 7 seg the number 0


when state1 =>
    tempB <= tempC(14 downto 0) & '0';   --left shift tempC(the output     register) save to tempB; this is the x2 multiplication
    tempD <= (tempA); -- output the input data(used for debugging)
    nextstate <= state2; 
    aout <= not "0110000"; -- output on the 7 seg the number 1

when state2 =>
     tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output      register) three times save to tempE; this is the x8 multiplication
    --tempC <=std_logic_vector( unsigned(tempE) + unsigned(tempD));   (TESTING)
     tempC <=std_logic_vector( ('0' & unsigned(tempE(14 downto 0))) + ('0' &   unsigned(tempD(14 downto 0)))); --add the first 15 bits of tempD and tempE(this      is how we multiply by 10)
    tempD <= (tempC); -- output the x10  output register
    nextstate <= state3; 
    aout <= not "1101101" ;  -- output on the 7 seg the number2 

when state3 =>
   -- tempC <= ('0' & tempC(14 downto 0)) + ('0' & tempA(14 downto 0)); (TESTING)
    tempC <= std_logic_vector( ('0' & unsigned(tempC(14 downto 0))) + ('0' & unsigned(tempA(14 downto 0)))); --add the 'Data' to the x10 shifted number.
    tempD <= (tempC);
    nextstate <= state0; 
    aout <= not "1111001"; -- output on the 7 seg the number3
 end case;
 end process;  
end behavioral; 

2 个答案:

答案 0 :(得分:0)

<强>答案

tempC在时钟进程中重置,然后获取组合过程中分配的新值。 不允许在两个不同的进程中为信号分配值。此外,组合过程的灵敏度列表缺少信号。

<强>观察:

  1. 为信号使用逻辑名称tempX非常混乱。我也想象你的BCD电路将被称为BUFF;)
  2. 检查组合过程的灵敏度列表。
  3. 谷歌如何构建状态机
  4. 非常重要的模拟您的设计(特别是对于大型设计) 看看在线的不同教程,例如Xilinx Vivado 2015.2 Simulation Tutorial
  5. 快乐调试

答案 1 :(得分:0)

好的,在一些评论和答案的帮助下,我能够让它发挥作用。以下是使用的代码。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity buff is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input
       Clock : in STD_LOGIC;
       Reset : in STD_LOGIC;
       Output : out STD_LOGIC_VECTOR (15 downto 0);
       aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output for current state.
end buff;

architecture Behavioral of buff is
type states is (state0, state1, state2, state3, state4);
signal currentstate, nextstate: states;
signal tempA: STD_LOGIC_VECTOR (3 downto 0);---used to store 'Data' for addition.
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data').
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register.
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's.
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data')
signal tempF: STD_LOGIC_VECTOR (15 downto 0);
begin
Process(Reset,clock)
Begin
if(Reset = '1') then
    currentstate <= state4;
    Output <= "0000000000000000"; -------reset state
elsif(clock'event and clock = '1') then  
      Output <= tempD ;--display the output of the buffer
      currentstate <= nextstate;  -- advance states   
end if;

end process;

process(currentstate)
begin
case currentstate is

when state0 =>
   tempA <= Data; -- load in 4 bit data intoi 16 bit register
    tempD(3 downto 0) <= tempA; --output the input data(used for debugging)
    nextstate <= state1;
    aout <= not "1111110"; -- output on the 7 seg the number 0


when state1 =>
    tempB <= (tempC(14 downto 0) & "0");   --left shift tempC(the output register) save to tempB; this is the x2 multiplication
    tempD <= (tempB); -- output the input data(used for debugging)
    nextstate <= state2; 
    aout <= not "0110000"; -- output on the 7 seg the number 1

when state2 =>
    tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output register) three times save to tempE; this is the x8 multiplication
    --tempF <=std_logic_vector( unsigned(tempE) + unsigned(tempB)); --(TESTING)
    tempF <=std_logic_vector( ('0' & unsigned(tempE(14 downto 0))) + ('0' & unsigned(tempB(14 downto 0)))); --add the first 15 bits of tempD and tempE(this is how we multiply by 10)
    tempD <= tempE; -- output the x10  output register
    nextstate <= state3; 
    aout <= not "1101101" ;  -- output on the 7 seg the number2 

 when state3 =>
    --tempC <=std_logic_vector( unsigned(tempC) + unsigned(tempA));
    tempC <= std_logic_vector( ('0' & unsigned(tempF(14 downto 0))) + ("000000000000" & unsigned(tempA))); --add the 'Data' to the x10 shifted number.
    tempD <= tempC;
    nextstate <= state0; 
    aout <= not "1111001"; -- output on the 7 seg the number3

  when state4 =>
    tempC <= "0000000000000000";
    tempA <= "0000";
    tempB <= "0000000000000000";
    tempD <= "0000000000000000";
    tempE <= "0000000000000000";
    tempF <= "0000000000000000";
    nextstate <= state0;
    aout <= not "0110011";

  end case;
 end process;  
 end behavioral;