如何在每列上置换矩阵列[VHDL]

时间:2016-12-29 16:23:48

标签: matrix vhdl permutation xilinx

我有一个小矩阵(5,8),我希望我的矩阵上每列的置换位取决于向量 col < =(2,4,0,1,3) ;它为相应的迭代计算每个新位置。每列的位将采用 col 向量给出的新位置。

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use ieee.numeric_std.all;
 use IEEE.math_real.all;
 use IEEE.math_complex.all;
 USE IEEE.std_logic_unsigned.ALL;
 use IEEE.std_logic_arith.ALL;

entity permutation is
 port(
 clk : in std_logic;
 rst : in std_logic;
 datain: in std_logic_vector(39 downto 0);
 dataout : out std_logic_vector(39 downto 0)
  );
 end permutation;

  architecture Behavioral of permutation is
  signal datain : std_logic_vector(39 downto 0) := "1011011101100110011001010110011001100110";
  signal temp: std_logic_vector(39 downto 0);
  type matrix is array(0 to 4,0 to 7) of std_logic;
  type table5 is array (0 to 4) of integer;
  signal mat1, matC: matrix;
  signal col: table5;
  signal pp:integer;
   signal j1,j2,i1,jx,ix,i2,i3,i4,per1,per2,ux: integer range 0 to 39;
  begin

  process(clk,rst)
  begin 

  if rst='1' then
  mat1<=(others=>(others=>'0'));
  elsif clk'event and clk='1' then      
      for j1 in 0 to 7 loop   --convert the vector datain to matrix mat1(5,8)
     for i1 in 0 to 4 loop 
     mat1(i1,j1)<=datain(j2);
      j2<=j2+1;
      end loop; 
      end loop; 
      end if;
  end process;

  process(clk, mat1)
  begin
  col<=(2,4,0,1,3); -- new places for each bit correspond to each iteration 
   -- permutation per column
  if (rising_edge(clk)) then    
  for ix in 0 to 4 loop
  for jx in 0 to 7 loop
     pp<=col(ux);
     if(jx = pp) then
    matC(per1,per2)<=mat1(ix,jx); --matC is the new matrix after permutation of each comumn's bits on mat1
   ux<=ux+1;
   per1 <= per1+1; 
     end if; 
     end loop; 
     per2 <= per2+1; 
     end loop;
    end if;

  --display      
 if(falling_edge(clk))then        
    for i3 in 0 to 7 loop
 for i2 in 0 to 4 loop  
temp(i4) <= matC(i2,i3);
i4<=i4+1;
end loop; 
end loop;   
end if;

end process;
dataout<=temp;
end Behavioral; 

0 个答案:

没有答案