VHDL：如何在RAM中读取/写入16位数据，每个地址8位

Question

我有一个VHDL代码，用于读取和写入8位数据到RAM，每个地址8位，但我需要更改代码，以便以8位读取/写入16位数据到RAM每个地址。 可以做些什么改变？

我的初始代码是：

{{1}}

Answer 1

试试此代码

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 entity RAM is
 port(address: in std_logic_vector(7 down to 0);
      datain: in std_logic_vector(15 downto 0);
      dataout: out std_logic_vector(15 downto 0);
      WE, CS, OE: in std_logic);
 end entity RAM;

architecture behavior6 of RAM is type RAM_type is array (255 down to 0) of std_logic_vector(15 downto 0); signal RAM1:memory:=(others=>"0000000000000000"); begin process (address, CS, WE, OE) variable a:integer range 0 to 255; begin a:=conv_integer(address); if (CS = '0') then if WE= '0' then RAM1(a)<=datain; end if; if WE= '1' and OE= '0' then dataout<=RAM1(a); end if; end if; end process; end behavior6;