Question

我正在尝试使用chisel3在不同的项目中自定义和使用Sodor处理器/ Rocket核心的ALU源文件。运行sbt test会给我以下错误。

[info] - should carry out proper arithmatic and logical operations (with verilator) *** FAILED ***

[info]   chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@7): Missing IO() wrapper

[info]   at chisel3.core.Binding$.checkSynthesizable(Binding.scala:185)

[info]   at chisel3.core.Bits.do_apply(Bits.scala:97)

[info]   at chisel3.core.Bits.do_apply(Bits.scala:109)

[info]   at RiscvIoT.ALU$.isSub(alu.scala:44)

[info]   at RiscvIoT.ALU.<init>(alu.scala:68)

[info]   at RiscvIoT.ALUTester$$anonfun$2$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(aluTest.scala:41)

[info]   at RiscvIoT.ALUTester$$anonfun$2$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(aluTest.scala:41)

[info]   at chisel3.core.Module$.do_apply(Module.scala:29)

[info]   at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:191)

[info]   at chisel3.Driver$$anonfun$elaborate$1.apply(Driver.scala:191)

按照关于凿子3 wiki的测试和调试指南，我认为初始错误位于第44行（isSub函数定义）。但是我无法弄清楚问题，我所做的一切都没有解决问题。为方便起见，我将在下面发布我的完整源文件。

import chisel3._
import chisel3.util._
import Common._

object ALU
{
  val SZ_ALU_FN = 4
  val ALU_X    = Bits(0)
  val ALU_ADD  = Bits(0)
  val ALU_SLL  = Bits(1)
  val ALU_XOR  = Bits(4)
  val ALU_OR   = Bits(6)
  val ALU_AND  = Bits(7)
  val ALU_SRL  = Bits(5)
  val ALU_SUB  = Bits(10)
  val ALU_SRA  = Bits(11)
  val ALU_SLT  = Bits(12)
  val ALU_SLTU = Bits(14)
  val ALU_COPY1= Bits(8)   

  def isMulFN(fn: Bits, cmp: Bits) = fn(1,0) === cmp(1,0)
  def isSub(cmd: Bits) = cmd(3)
  def isSLTU(cmd: Bits) = cmd(0)
}
import ALU._

class ALUIO extends Bundle {
  val xprlen = 32
  val fn = Bits(INPUT, SZ_ALU_FN)
  val in2 = UInt(INPUT, xprlen)
  val in1 = UInt(INPUT, xprlen)
  val out = UInt(OUTPUT, xprlen)
  val adder_out = UInt(OUTPUT, xprlen)
}

class ALU extends Module
{
  val io = new ALUIO
  val xprlen = 32
  val msb = xprlen-1

  // ADD, SUB
  val sum = io.in1 + Mux(isSub(io.fn), -io.in2, io.in2)

  // SLT, SLTU
  val less  = Mux(io.in1(msb) === io.in2(msb), sum(msb),
              Mux(isSLTU(io.fn), io.in2(msb), io.in1(msb)))

  // SLL, SRL, SRA
  val shamt = io.in2(4,0).toUInt
  val shin_r = io.in1(31,0)
  val shin = Mux(io.fn === ALU_SRL  || io.fn === ALU_SRA, shin_r, Reverse(shin_r))
  val shout_r = (Cat(isSub(io.fn) & shin(msb), shin).toSInt >> shamt)(msb,0)
  val shout_l = Reverse(shout_r)

  val bitwise_logic =
    Mux(io.fn === ALU_AND, io.in1 & io.in2,
    Mux(io.fn === ALU_OR,  io.in1 | io.in2,
    Mux(io.fn === ALU_XOR, io.in1 ^ io.in2,
                       io.in1))) // ALU_COPY1

//  val out64 =
  val out_xpr_length =
    Mux(io.fn === ALU_ADD || io.fn === ALU_SUB,  sum,
    Mux(io.fn === ALU_SLT || io.fn === ALU_SLTU, less,
    Mux(io.fn === ALU_SRL || io.fn === ALU_SRA,  shout_r,
    Mux(io.fn === ALU_SLL,                       shout_l,
    bitwise_logic))))

  io.out := out_xpr_length(31,0).toUInt
  io.adder_out := sum
}

Answer 1

抛出的异常：chisel3.core.Binding$BindingException: 'this' (chisel3.core.UInt@7): Missing IO() wrapper是因为在chisel3中，io必须包装在IO（...）中

在文档中可能有点隐藏（参见https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2#deprecated-usage）

要修复，请将ALU中的io声明更改为：

val io = IO(new ALUIO)

您还应该将ALUIO更改为：

class ALUIO extends Bundle {
  val xprlen = 32
  val fn = Input(Bits(SZ_ALU_FN.W))
  val in2 = Input(UInt(xprlen.W))
  val in1 = Input(UInt(xprlen.W))
  val out = Output(UInt(xprlen.W))
  val adder_out = Output(UInt(xprlen.W))
}

虽然我认为旧的方式已被弃用而不是错误。

sodor /火箭核心ALU中的凿子测试错误

1 个答案: