Question

希望使用顶级verilog 2005模块实现PWM序列：

  module PWM_ENHANCER (

    input clk,
    input rst,
    input sent,

    //input
    input [7:0] BUF,                                        //BUFFER - The PWM reads from it only when 'sent' signal is received, and the current run is done.

    //output
    output reg PWM_WAIT,
    output reg PWM_OUT
    );
reg         [7:0] SAMPLE;
reg     [7:0]   counter;
reg     WORK;

always@(posedge clk or negedge rst)

begin 
    if( !rst )
    begin
      WORK <= 1'b0;                             //When receiving a reset, everything zeroes.
        counter <= 8'b0;
        PWM_WAIT <= 1'b1;
        SAMPLE <= 8'b0;
        PWM_OUT <= 1'b0;
    end
    else if (sent == 1 && WORK == 0) 
    begin               //If the pwm was OFF, and i received sign from the array, i start running PWM.
        SAMPLE <= BUF;
        WORK <= 1'b1;
        PWM_WAIT <= 1'b0;
    end
    else if(WORK == 1) 
    begin                               //The running block - sending '0' and '1' as needed.
            if ( (counter <= SAMPLE) && (SAMPLE != 0) ) 
            begin
                PWM_OUT <= 1'b1;
                counter = counter + 1'b1;
            end

            else if ( counter > SAMPLE )
            begin
                if ( counter == 8'b11111111 ) 
                begin
                    counter <= 8'b0;
                    WORK <= 1'b0;
                end

                else 
                begin
                    counter = counter + 1'b1;
                    PWM_OUT <= 1'b0;
                end
            end;
            if(counter == 200) 
            begin                       // 50 cycles before the end, PWM sends acknowledge for the array to send the next sample.
                PWM_WAIT <= 1'b1;
            end
    end     

    else 
    begin 
        ;                                                           // if NOT receiving 'sent' from the array - the PWM does nothing.
    end

end 
endmodule

编译时

收到错误：

“不允许在顶部设计单元内部生成复位'PWM_ENHANCER'。”

如何在@always语句中包含重置？

Answer 1

两种可能性（两种综合相关）：

您的合成器需要额外的手持式才能进行异步复位

if(!rst) begin
  WORK <= 1'b0;
  counter <= 8'b0;
  PWM_WAIT <= 1'b1;
  SAMPLE <= 8'b0;
  PWM_OUT <= 1'b0;
end
else begin
  // other logic in here
end

您的标准单元库缺少具有异步重置/预设的触发器。 FPGA具有异步复位/预置的有限数量的触发器。有些FPGA没有。如果是这种情况，可以做的最简单的事情是将异步重置更改为同步重置，方法是将总是阻塞的顶部更改为always@(posedge clk)（省略or negedge rst）。如果您使用的是FPGA，则可能需要添加initial块来初始化寄存器的默认值。

内部生成重置verilog 2005

1 个答案: