端口映射仅适用于某些实体

Question

我以为我得到了这个映射的东西，但它似乎我不...所以，我有下面的代码有顶部实体（circuito）有控制和数据路径实体里面。当我合成项目时，它发出一堆警告（0错误），基本上说数据路径（输入和输出）中的所有端口都没有连接（“[Synth 8-3331]设计数据路径有未连接的端口res [31]”等等所有端口）实际上，它并没有连接设计中的端口，甚至删除了数据路径实体，将控制实体保留在circuito中（因此控制没有问题）。两个实体的reset和clk端口相同，但它不会将该端口映射到数据路径，仅用于控制。帮帮我们，怎么了？如果您需要更多代码，请告诉我。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity circuito is
  port (
    clk, reset: in std_logic;
    x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
    res : out signed(31 downto 0);
    done : out std_logic
    );
end circuito;

architecture Behavioral of circuito is
  component control
    port(
     clk, reset, done : in std_logic;
     e_in : out std_logic;
     e_out : out std_logic;
     e_inter : out std_logic_vector (4 downto 0);
      mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : out std_logic_vector (1 downto 0);
     mux_sel4, mux_sel7 : out std_logic );
  end component;
    component datapath
    port(
         x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
              clk, reset : in std_logic;
              e_in : in std_logic;
              e_out : in std_logic;
              e_inter : in std_logic_vector (4 downto 0);
              mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : in std_logic_vector (1 downto 0);
              mux_sel4, mux_sel7 : in std_logic;
              res : out signed (31 downto 0);
              done : out std_logic );
  end component;

  signal e_in : std_logic;
  signal e_inter : std_logic_vector(4 downto 0);
  signal finish, e_out : std_logic;
  signal mux_sel1, mux_sel2, mux_sel3, mux_sel5, mux_sel6 : std_logic_vector (1 downto 0);
  signal mux_sel4, mux_sel7 : std_logic;

begin

inst_datapath: datapath port map(
    clk => clk,
    reset => reset,
    done => finish,
    e_in => e_in,
    e_out => e_out,
    e_inter => e_inter,
    mux_sel1 => mux_sel1,
    mux_sel2 => mux_sel2,
    mux_sel3 => mux_sel3,
    mux_sel4 => mux_sel4,
    mux_sel5 => mux_sel5,
    mux_sel6 => mux_sel6,
    mux_sel7 => mux_sel7,
    res => res,
    x => x,
   c0 => c0,
   c1 => c1,
   c2 => c2,
   c3 => c3,
   c4 => c4,
   c5 => c5,
   c6 => c6,
   c7 => c7
   );
inst_control: control port map(
    clk => clk,
    reset => reset,
    done => finish,
    e_in => e_in,
    e_out => e_out,
    e_inter => e_inter,
    mux_sel1 => mux_sel1,
    mux_sel2 => mux_sel2,
    mux_sel3 => mux_sel3,
    mux_sel4 => mux_sel4,
    mux_sel5 => mux_sel5,
    mux_sel6 => mux_sel6,
    mux_sel7 => mux_sel7
    );    

end Behavioral;

使用以下方法实现datapath组件：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;


--Datapath entity
entity datapath is
    port ( x, c0, c1, c2, c3, c4, c5, c6, c7 : in signed(6 downto 0);
           clk, reset : in std_logic;
           e_in : in std_logic;
           e_out : in std_logic;
           e_inter : in std_logic_vector (4 downto 0);
           mux_sel1, mux_sel2, mux_sel3, mux_sel5,  mux_sel6  : in std_logic_vector (1 downto 0);
           mux_sel4, mux_sel7 : in std_logic;
           res : out signed (31 downto 0);
           done : out std_logic       
           );
end datapath;

architecture Behavioral of datapath is
    signal Rx, Rc0, Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7 : signed(6 downto 0) := (others => '0');
    signal Rout : signed(31 downto 0) := (others => '0');
    signal R1, R2, R3, R4, Rx2 : signed(31 downto 0) := (others => '0');
    signal add1, add2, mul1, mul2 : signed(31 downto 0) := (others => '0');
    signal mux1, mux2, mux3, mux4, mux5, mux6, mux7 : signed(31 downto 0) := (others => '0');

begin
--"Fixed" Input Registers:

--Register Rc0
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc0 <= "0000000";
            elsif e_in = '1'then
                Rc0 <= c0;
            end if;
        end if;
    end process;

--Register Rc1
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc1 <= "0000000";
            elsif e_in = '1'then
                Rc1 <= c1;
            end if;
        end if;
    end process;

--Register Rc2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc2 <= "0000000";
            elsif e_in = '1'then
                Rc2 <= c2;
            end if;
        end if;
    end process;

--Register Rc3
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc3 <= "0000000";
            elsif e_in = '1'then
                Rc3 <= c3;
            end if;
        end if;
    end process;

--Register Rc4
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc4 <= "0000000";
            elsif e_in = '1'then
                Rc4 <= c4;
            end if;
        end if;
    end process;

--Register Rc5
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc5 <= "0000000";
            elsif e_in = '1'then
                Rc5 <= c5;
            end if;
        end if;
    end process;

--Register Rc6
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc6 <= "0000000";
            elsif e_in = '1'then
                Rc6 <= c6;
            end if;
        end if;
    end process;

--Register Rc7
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rc7 <= "0000000";
            elsif e_in = '1'then
                Rc7 <= c7;
            end if;
        end if;
    end process;

--Register Rx
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rx <= "0000000";
            elsif e_in = '1'then
                Rx <= x;
            end if;
        end if;
    end process;

--Intermediate Registers:

    --Register R1
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R1 <= X"00000000";
            elsif e_inter(0) = '1'then
                R1 <= mul1;
            end if;
        end if;
    end process;

    --Register R2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R2 <= X"00000000";
            elsif e_inter(1) = '1'then
                R2 <= mul2;
            end if;
        end if;
    end process;

    --Register R3
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R3 <= X"00000000";
            elsif e_inter(2) = '1'then
                R3 <= add1;
            end if;
        end if;
    end process;

    --Register R4
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                R4 <= X"00000000";
            elsif e_inter(3) = '1'then
                R4 <= add2;
            end if;
        end if;
    end process;

    --Register Rx2
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rx2 <= X"00000000";
            elsif e_inter(4) = '1'then
                Rx2 <= mul1;
            end if;
        end if;
    end process;

    --Multiplexer1
    mux1 <= resize(Rc7, mux1'length) when mux_sel1 = B"00" else
            resize(Rx, mux1'length) when mux_sel1 = B"01" else
            resize(R3, mux1'length) when mux_sel1 = B"10" else
            resize(Rx2, mux1'length) ;

    --Multiplexer2
    mux2 <= resize(Rx, mux2'length) when mux_sel2 = B"00" else
            resize(Rx2, mux2'length) when mux_sel2 = B"01" else
            resize(R1, mux2'length) ;

    --Multiplexer3
    mux3 <= resize(Rc7, mux3'length) when mux_sel3 = B"00" else
            resize(Rc3, mux3'length) when mux_sel3 = B"01" else
            resize(Rc1, mux3'length) when mux_sel3 = B"10" else
            resize(R3, mux3'length) ;

    --Multiplexer4
    mux4 <= resize(Rx, mux4'length) when mux_sel4 = '0' else
            resize(Rx2, mux4'length) when mux_sel4 = '1';

    --Multiplexer5
    mux5 <= resize(R1, mux5'length) when mux_sel5 = B"00" else
            resize(Rc2, mux5'length) when mux_sel5 = B"01" else
            resize(R4, mux5'length) when mux_sel5 = B"10" else
            resize(R3, mux5'length) ;

    --Multiplexer6
    mux6 <= resize(Rc6, mux6'length) when mux_sel6 = B"00" else
            resize(R2, mux6'length) when mux_sel6 = B"01" else
            resize(Rx2, mux6'length);

    --Multiplexer7
    mux7 <= resize(Rc4, mux7'length) when mux_sel7 = '0' else
            resize(Rc0, mux7'length) when mux_sel7 = '1';


    --Adder1
    add1 <= resize(mux5 + mux6, add1'length) ;

    --Adder2
    add2 <= resize(R2 + mux7, add1'length) ;

    --Multiplier1
    mul1 <= resize(mux1 * mux2, mul1'length) ;

    --Multiplier1
    mul2 <= resize(mux3 * mux4, mul2'length) ;


    --"Fixed" Output Register:

    --Register Rout
    process (clk, reset)
    begin
        if clk'event and clk = '1'then
            if reset = '1' then
                Rout <= X"00000000";
            elsif (e_out = '1') then
                Rout <= R3;
                done <= '1';
            end if;
        end if;
    end process;

    res <= Rout;

end Behavioral;

编辑：做了一些改动，不知道什么有效，但现在只有c5端口没有连接，无论是在circuito还是数据路径

Answer 1

从评论中，e_inter的输出control始终为全零。在此过程中出现错误，res中的信号datapath就会被分配：

if clk'event and clk = '1'then
    if reset = '1' then
        Rout <= X"00000000";
    elsif (e_out = '1') then
        Rout <= R3;
        done <= '1';
    end if;
end if;

...

res <= Rout;

R3因此被驱动：

if clk'event and clk = '1'then
    if reset = '1' then
        R3 <= X"00000000";
    elsif e_inter(2) = '1'then
        R3 <= add1;
    end if;
end if;

从这两个代码段中，我们可以看到，如果e_inter(2)始终为'0'，则可以对res进行的唯一分配是将其重置为全零。由于此端口是常量，因此工具将对其进行优化。

诊断此类问题的基本方法是查看警告。通常会有很多无用的警告，这可能会使这个过程变得乏味，但您应该能够使用消息过滤将它们细化一点，从而显示有用的消息。在这种情况下，应该有消息告诉你逻辑和/或信号由于常数传播或相似而被删除。