所以我已经从Vivado 2015.4升级到2016.2。我使用Vivado编译加密IP的模拟文件。当我启动Modelsim 10.4时,会出现一个新错误:
sources_1/ip/output_buffer/sim/output_buffer.v(289): Module 'fifo_generator_v13_1_1' is not defined.
我注意到的第一件事是,在我的项目流程中,生成的模拟文件现在是verilog,因为我通常模拟VHDL,这可能是我的问题的根源。
首先,我编译各种库,例如fifo_generator库:
compile_simlib -simulator questa
然后我生成模拟文件:
import_files -norecurse -fileset sources_1 cgen/output_buffer/output_buffer.xci
upgrade_ip [get_ips output_buffer]
generate_target simulation [get_files output_buffer.xci]
export_simulation -simulator questa -of_objects [get_files output_buffer.xci]
exec echo exit | vsim -c -do top/top.srcs/sources_1/ip/output_buffer_sim/questa/compile.do -modelsimini modelsim.ini
我的modelsim.ini文件然后映射这些库:
[Library]
fifo_generator_v13_1_1 = msim/fifo_generator_v13_1_1
output_buffer = top/top.srcs/sources_1/ip/output_buffer/questa
最后,我的.tcl脚本将构建项目并添加模拟文件:
vlog top / top.srcs / sources_1 / ip / output_buffer / sim / output_buffer.v
然而,当我启动我的项目时,它抱怨它无法找到fifo_generator。任何想法为什么会这样?
根据要求,生成的compile.do:
vlib work
vlib msim
vlib msim/xil_defaultlib
vlib msim/xpm
vlib msim/fifo_generator_v13_1_1
vmap xil_defaultlib msim/xil_defaultlib
vmap xpm msim/xpm
vmap fifo_generator_v13_1_1 msim/fifo_generator_v13_1_1
vlog -work xil_defaultlib -64 -sv \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv" \
vcom -work xpm -64 \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/hdl/fifo_generator_v13_1_rfs.vhd" \
vlog -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/hdl/fifo_generator_v13_1_rfs.v" \
vlog -work xil_defaultlib -64 \
"../../output_buffer/sim/output_buffer.v" \
vlog -work xil_defaultlib "glbl.v"
它复制modelsim.ini文件,然后您可以运行这些命令中的一个或全部三个。实际上我想做的就是编译所以我有一个可以在以后的模拟中使用的对象,即创建的output_buffer.v
文件。
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee -a elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./output_buffer.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
答案 0 :(得分:1)
模块fifo_generator_v13_1_1已编译到fifo_generator_v13_1_1库,我认为这可能是个问题。尝试将-L fifo_generator_v13_1_1
添加到您的vsim命令中以搜索此库中的模块。