是否有可能在Chisel中生成sum并在一行中携带类似于Verilog中的此代码?
module Adder_with_carry(
input [3:0] A,
input [3:0] B,
input Carry_in,
output [3:0] Sum,
output Carry_out
);
assign {Carry_out, Sum} = A + B + Carry_in;
endmodule
我正在使用此代码
class Adder extends Module{
val io = new Bundle{
val a = UInt(INPUT, 3)
val b = UInt(INPUT, 3)
val carry_in = UInt (INPUT, 1)
val sum = UInt (OUTPUT, 2)
val carry_out = UInt(OUTPUT, 1)
}
val SUM = io.a + io.b + io.carry_in;
io.carry_out := SUM(2)
io.sum := SUM(1,0)
}
但我认为如果有一个单行的话会更方便。