Question

这是一个使用两个4位移位寄存器的8位移位寄存器模块。 4位寄存器模块工作正常。（暂时只测试这个换班）

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这是测试平台。

module shift_reg_8 (Out,In,shift_left,shift_right,s0,s1,enable,clock);

    output [7:0] Out;
    wire [3:0]Least_Out,Most_Out;                

    input  [7:0] In;                
    wire [3:0]Least_In,Most_In;
    reg temp;

    initial
    temp  = In[4];

    assign {Most_In,Least_In} = In;
    input shift_left,shift_right,enable,s0,s1,clock;        

    shift_reg least_sig_reg(Least_Out,Least_In,shift_left,shift_right,s0,s1,enable,clock);                
    shift_reg most_sig_reg(Most_Out,Most_In,shift_left,shift_right,s0,s1,enable,clock);         

    assign Out = {Most_Out,Least_Out};
    assign Out[3] = temp;

endmodule

endmodule

这会在模拟时给出这样的输出。

测试1（右移）：INPUT = 01101110，S1 = 1，S0 = 0，SR = 1，OUTPUT = 1011x111

可能是什么问题？

这里是shift_reg代码......

module stimulus;


reg [7:0]INPUT;
reg ENABLE,CLOCK,S0,S1,SL,SR;   

wire [7:0] OUTPUT;  

shift_reg_8 my8shiftreg(OUTPUT,INPUT,SL,SR,S0,S1,ENABLE,CLOCK);       // SL = Shift_Left, SR = Shift_Right, SO,S1 = Controls 

initial
begin

    CLOCK = 1'b0;

    INPUT = 8'b01101110; ENABLE = 1;S0 = 0;S1 = 1;SL = 0;SR = 1;
    #14 $display("Test 1 (Right Shift): INPUT = %b, S1 = %b, S0 = %b, SR = %b, OUTPUT = %b\n",INPUT,S1,S0,SR,OUTPUT);

end

always
#5 CLOCK = ~CLOCK;

    initial
#100 $stop;

endmodule

Answer 1

您要分配[3]两次。

assign Out = {Most_Out,Least_Out};  // Assigns all 8 bits
assign Out[3] = temp;  //  Assigns bit 3 again.

多个驱动程序导致未知状态。

Verilog输出给出了＆＃39; x＆＃39;

1 个答案: