Question

我正在制作有4个32位加法器的加法器数组..

a0 + b0导致dout0，同样为a1,2,3和b1,2,3。

但是如下图所示，d0，d1，d2，d3始终为0或X. 我该如何解决这个问题？

module adder_array(
    cmd,
    ain0, ain1, ain2, ain3,
    bin0, bin1, bin2, bin3,
    dout0, dout1, dout2, dout3,
    overflow);

    input [2:0] cmd;
    input [31:0] ain0, ain1, ain2, ain3;    
    input [31:0] bin0, bin1, bin2, bin3;
    output reg [31:0] dout0, dout1, dout2, dout3;
    output [3:0] overflow;

    wire [31:0] a[3:0];
    wire [31:0] b[3:0];
    wire [31:0] d[3:0];
    wire ovf[3:0];

这是我用于加法器的32位添加模块

module my_add #(parameter BITWIDTH = 32)
(

    input [BITWIDTH-1:0] ain,
    input [BITWIDTH-1:0] bin,
    output [BITWIDTH-1:0] dout,
    output overflow
);

    assign {overflow, dout} = ain + bin;

endmodule


    assign {a[0],a[1],a[2],a[3]} = {ain0,ain1,ain2,ain3};
    assign {b[0],b[1],b[2],b[3]} = {bin0,bin1,bin2,bin3};
    assign {d[0],d[1],d[2],d[3]} = {dout0,dout1,dout2,dout3};
    assign overflow = {ovf[3], ovf[2], ovf[1], ovf[0]};

    parameter size = 4;


    genvar i;
    generate for(i = 0 ; i < size - 1 ; i = i + 1)
     begin:adder
      if (i == 0) begin 
       my_add adder(.ain(a[0]), .bin(b[0]), .dout(d[0]), .overflow(ovf[0])); end
      else if (i == size - 1 ) begin
       my_add adder(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
      end
      else begin
       my_add adder(.ain(a[i]), .bin(b[i]), .dout(d[i]), .overflow(ovf[i]));
      end
     end
    endgenerate

always @(cmd) begin    

    case(cmd)

    3'b000 : begin dout0 = d[0]; dout1 = 0; dout2 = 0; dout3 = 0; end
    3'b001 : begin dout0 = 0; dout1 = d[1]; dout2 = 0; dout3 = 0; end
    3'b010 : begin dout0 = 0; dout1 = 0; dout2 = d[2]; dout3 = 0; end
    3'b011 : begin dout0 = 0; dout1 = 0; dout2 = 0; dout3 = d[3]; end
    3'b100 : begin dout0 = d[0]; dout1 = d[1]; dout2 = d[2]; dout3 = d[3]; end
    default : begin dout0 = 0; dout1 = 0; dout2 = 0; dout3 = 0; end
    endcase
    end

endmodule

它是我的测试平台模块

module test_bench_32b_adder #(
    parameter BITWIDTH = 32
) ();

    reg [2:0] cmd;
    reg [31:0] ain0, ain1, ain2, ain3;
    reg [31:0] bin0, bin1, bin2, bin3;
    wire [31:0] dout0, dout1, dout2, dout3;
    wire [3:0] overflow;

    integer i;
    initial begin
        for(i = 0; i < 32; i = i + 1) begin
            ain0 = $urandom%(2**31);
            ain1 = $urandom%(2**31);
            ain2 = $urandom%(2**31);
            ain3 = $urandom%(2**31);
            bin0 = $urandom%(2**31);
            bin1 = $urandom%(2**31);
            bin2 = $urandom%(2**31);
            bin3 = $urandom%(2**31);
            cmd = $urandom%(2**3);
            #10;
          end
        end

    adder_array  ADDER_ARRAY(
        .cmd(cmd),
        .ain0(ain0),
        .ain1(ain1),
        .ain2(ain2),
        .ain3(ain3),        
        .bin0(bin0),
        .bin1(bin1),
        .bin2(bin2),
        .bin3(bin3),
        .dout0(dout0),
        .dout1(dout1),
        .dout2(dout2),
        .dout3(dout3),
        .overflow(overflow)
        );
endmodule

波的输出可以在下面看到，

Answer 1

这条线似乎引起了＆＃39; X＆＃39;您一直在观察，尝试删除此行

assign {d[0],d[1],d[2],d[3]} = {dout0,dout1,dout2,dout3};

来自您的模块。

这里通过上面提到的行，你试图将输出分配给一个有另一个来自my_add模块的驱动程序的导线，导致输出到未知＆＃34; X＆＃34;状态，

总结如此assign d[0]=dout和assign dout =d[0]尝试同时分配值，从而产生＆＃39; X＆＃39;在公共汽车上。

当使用generate for和case时，verilog输出给出x或0

1 个答案: