Question

我想在记录中约束变量。此变量是 test_vector 中的 id_dd （记录）

type test_vector is record 
            id_dd : integer; 
            stimulus : bit_vector; 
            response : bit_vector; 
        end record test_vector; 

type test_time is record 
            stimulus_time : time; 
            response_delay : delay_length; 
        end record test_time; 

type test_application is record 
            test_to_apply : test_vector; 
            application_time : test_time; 
        end record test_application; 

subtype schedule_test is test_application (test_to_apply (  id_dd (0 to 100) ,
                                                            stimulus (0 to 7),
                                                            response(0 to 9)));

Modelsim错误是：

Constraint for record element "test_vector.id_dd" (at depth 1) cannot apply to non-composite type (std.STANDARD.INTEGER)

如何使用子类型约束id_dd？

Answer 1

根据LRM：

record_constraint ::=
  ( record_element_constraint { , record_element_constraint } )

record_element_constraint ::=
  record_element_simple_name element_constraint

element_constraint ::=
  array_constraint
  | record_constraint

如您所见，元素约束不能是range_constraint，只能是array_constraint或record_constraint。我没有找到关于这个限制的解释。这可能是EDA供应商严格执行的遗漏吗？还是有另一个好理由？我有兴趣知道。

如何在VHDL 2008中约束整数

1 个答案: