Question

VHDL-2008定义

type integer_vector is array (natural range <>) of integer

它可以用来创建无约束整数的数组：

signal sUnconsrainedIntA : integer_vector(0 to 1) := (others => 0);

但是，如何声明约束整数数组，例如：

-- does not work:
-- signal sConstrainedTestIntA : integer_vector(0 to 1) range 0 to 3 := (others => 0);
-- ** Error: filetest.vhd(65): Range constraints cannot be applied to array types.
-- ** Error: filetest.vhd(65): Range expression is type Integer; expecting type std.STANDARD.INTEGER_VECTOR

-- What you can do is:
type my_int_array is array (natural range <>) of integer range 0 to 3;
signal sConstrainedIntA : my_int_array(0 to 1) := (others => 0);

有没有办法在没有自定义类型的情况下约束数组中的整数？

Answer 1

VHDL 2008支持包通用参数。你可以尝试类似的东西：

package foo_pkg is
    generic(l, h: integer);
    subtype my_integer is integer range l to h;
    type my_integer_vector is array(natural range <>) of my_integer;
end package foo_pkg;

package foo_pkg_m17_p39 is new work.foo_pkg
    generic map(l => -17, h => 39);

package foo_pkg_p57_p134 is new work.foo_pkg
    generic map(l => 57, h => 134);

entity foo is
    port(iv1: work.foo_pkg_m17_p39.my_integer_vector(0 to 7);
         iv2: work.foo_pkg_p57_p134.my_integer_vector(0 to 7)
     );
end entity foo;

不是非常用户友好，因为每个整数约束需要一个包实例化声明。但是我发现这就像你要求的那样......

即使它看起来比您预期的更复杂，它仍然允许您为my_integer_vector的所有变体分解自定义代码。

如何约束VHDL-2008 integer_vector？

1 个答案: