Question

我有这个简单的测试代码（test.v）来生成编译错误。

`timescale 1ns/10ps

`define START 'h10000000;
`define WIDTH 800
`define HEIGHT 600

module test;
integer ifm_addr;
integer ifm_idx;

initial begin
    ifm_idx = 0;
    ifm_addr = `START + ifm_idx*4*`HEIGHT*`WIDTH;
end

initial begin
#1000;
$finish;
end

endmodule

当我运行ncvlog test.v时，我收到此错误，我无法弄清楚错误。

ncvlog: 12.20-s008: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
    ifm_addr = `START + ifm_idx*4*`HEIGHT*`WIDTH;
                      |
ncvlog: *E,NOTSTT (test.v,11|19): expecting a statement [9(IEEE)].
    ifm_addr = `START + ifm_idx*4*`HEIGHT*`WIDTH;
                               |
ncvlog: *E,MISEXX (test.v,11|28): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].

请帮忙！

编辑：错误是因为;末尾的define START 'h10000000。它会在+块中的语句后显示initial。

Answer 1

您尚未定义ifm_idx。

module test;
  integer ifm_addr;
  integer ifm_idx;


  initial begin
    ifm_addr = `START + ifm_idx*4*`HEIGHT*`WIDTH;
  end

NOTSTT错误：期待verilog中的语句

1 个答案: