实例化类时，systemverilog中的“期望描述”错误

Question

我认为我的Quartus坏了，但我希望语法错误（semi-colons看起来正确）。我从here偷了这个确切的代码，因为它不起作用，我希望有人知道在Quartus中要检查什么来编译它。

代码：

class C;
  int x;
  task set (int i);
    x = i;
  endtask
  function int get;
    return x;
  endfunction
endclass

错误：

错误文字：

Error (10170): Verilog HDL syntax error at enable_logic_tb.sv(42) near text: "class";  expecting a description. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Answer 1

Quartus不会合成类。 class构造仅用于模拟。