Question

基本上我有一个unsigned数组和一个将数组中第一个值增加1的进程。这很好用，直到我实现了异步重置，它将数组的元素设置为0.奇怪的是，即使从未达到异步重置的代码，它也会使我的其余代码不再起作用。这是我的代码：

use work.datentyp.all;

library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
entity vektoruhr is
    port (

        clk, reset : in std_logic ;
    );
end vektoruhr;
architecture v1 of vektoruhr is

    signal internal_stamp : vektor := (others => (others => '0'));

begin

process(clk)
    begin
        if(rising_edge(clk)) then
            internal_stamp(0) <= internal_stamp(0) + 1;
        end if;
    end process;

    process(reset)
    begin
    if(rising_edge(reset)) then
        report "reset triggered"; 
        -- internal_stamp <= (others => (others => '0'));
        alarm <= '0';
    end if;
    end process;
end v1;

如您所见，行

 -- internal_stamp <= (others => (others => '0'));

被注释掉了。像这样，一切正常。但是如果我删除 - ，则第一个元素的值首先是00，然后在第一个增量后变为0x，在第二个变量后变为xx。之后它停留在xx。复位输入从开始就设置为'0'，永远不会改变。

Answer 1

VHDL是一种硬件描述语言。每个过程代表一块硬件。您正在从两个进程中驱动信号internal_stamp。你有一个短路。当你注释掉这行

时

 internal_stamp <= (others => (others => '0'));

这导致internal_stamp仅从一个进程驱动。因此没有短路和没有'X'值。

如果您正在编写顺序逻辑，则应该坚持使用模板。下面是一个这样的顺序逻辑模板，带有异步复位，所有综合工具都应该理解：

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset ='1' then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;

以下是没有异步复位的顺序逻辑模板：

process(clock)  -- nothing else should go in the sensitivity list
begin
    if rising_edge(clock) then  -- or falling_edge(clock)
        -- put the synchronous stuff here (including the reset)
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;

因此，您应该使用一个进程而不是两个进程编写逻辑代码。假设您需要异步重置：

process(clk, reset)
    begin
        if reset = '1' then
          report "reset triggered"; 
          internal_stamp <= (others => (others => '0'));
          alarm <= '0';
        elsif(rising_edge(clk)) then
          internal_stamp(0) <= internal_stamp(0) + 1;
        end if;
    end process;

但是，如果您想要同步重置：

process(clk)
    begin
      if(rising_edge(clk)) then
        if reset = '1' then
          report "reset triggered"; 
          internal_stamp <= (others => (others => '0'));
          alarm <= '0';
        else
          internal_stamp(0) <= internal_stamp(0) + 1;
        end if;
    end process;

VHDL奇怪的一系列无符号行为

1 个答案: