我正在尝试使用verilog在virtex 5 FPGA上实现RSA。 Xilinx ISE日志不具有描述性。我使用的是CORDIC 4.0 IP内核和随机数生成器。过去一周我一直在研究这个问题，但我似乎无法直截了当。
主要文件
`include "GARO.v"
module RSA_Encryption(RST_N,CLOCK,CTEXTPUB,RANDP,RANDQ,RANDE,PRIME_CHECK,PRIME_CHECKED,MESSAGE,RECEIVED);
//******************************************************
//Declarations
//******************************************************
reg RST_N;
input wire CLOCK;
input wire [31:0] PRIME_CHECKED;
output wire [31:0] PRIME_CHECK;
input wire [31:0] RANDP;
input wire [31:0] RANDQ;
input wire [31:0] RANDE;
integer randp;
integer randq;
integer phi;
integer e;
integer d;
integer mod = 0;
integer i = 0;
input wire [31:0] MESSAGE;
input wire [31:0] RECEIVED;
integer message;
integer received;
integer sqroot;
output wire [31:0] CTEXTPUB;
RST_N = 1;
d = 1;
//******************************************************
//******************************************************
//Calling random number generator module to get random numbers via wires: RANDP, RANDQ and RANDE
//******************************************************
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDP);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDQ);
fibonacci_lfsr_nbit(CLOCK,RST_N,RANDE);
//******************************************************
//******************************************************
//Assigning random numbers from respective wires to integer variables randp, randq and e
//******************************************************
e = RANDE;
randp = RANDP;
randq = RANDQ;
//******************************************************
//******************************************************
//Check whether randp is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randp);
for(i = 0 ; i <= sqroot ; i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randp = RANDP;
end while(1);
//******************************************************
//******************************************************
//Check whether randq is prime or not
//******************************************************
do begin
Square_Root_CORDIC_Core_IP (CLOCK,sqroot,randq);
for(int i = 0;i<=sqroot,i++)
begin
if((sqroot%i) == 0)
begin
break;
end
end
break;
randq = RANDQ;
end while(1);
//*******************************************************
//*******************************************************
//Computing 'phi'
//*******************************************************
phi = (randp-1)(randq-1);
//*******************************************************
//*******************************************************
//Selecting 'e'
//*******************************************************
do begin
e = RANDE;
end while(e < phi && e > 1);
//*******************************************************
//*******************************************************
//Checking if gcd(e,phi) is 1
//*******************************************************
do begin
rem = phi%e;
if(rem == 0 && e == 1)
begin
break;
end
else
begin
do begin
e = RANDE;
end while(e > phi && e > 1);
end
phi = e;
e = rem;
end while(1);
//***********************************************
//***********************************************
//Computing 'n'
//***********************************************
n = randp*randq;
//***********************************************
//***********************************************
//Calculating 'd'
//***********************************************
do begin
mod = (d*e)%phi;
d = d+1;
end while(mod != 1);
//***********************************************
//***********************************************
//Computing Ciphertext using public key i.e (n,e)
//***********************************************
message = MESSAGE;
do begin
message = message*message;
e--;
end while(e != 0);
CTEXTPUB = message%n;
//***********************************************
//***********************************************
//Decrypting ciphertext using private key i.e (n,d)
//***********************************************
received = RECEIVED;
do begin
received = received*received;
d = d-1;
end while (d != 0);
received = received%n;
//************************************************
endmodule
随机数发生器
module fibonacci_lfsr_nbit
#(parameter BITS = 32)
(
input clk,
input rst_n,
output reg [31:0] data
);
reg [31:0] data_next;
always_comb begin
data_next = data;
repeat(BITS) begin
data_next = {(data_next[31]^data_next[1]), data_next[31:1]};
end
end
always_ff @(posedge clk or negedge rst_n) begin
if(!rst_n)
data <= 32'h1f1f;
else
data <= data_next;
end
end
endmodule
这里是IP CORE API
`timescale 1 ns/1 ps
module Square_Root_CORDIC_Core_IP (
clk, x_out, x_in
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] x_out;
input [31 : 0] x_in;
日志
Started : "Behavioral Check Syntax".
Determining files marked for global include in the design...
Running vlogcomp...
Command Line: vlogcomp -work isim_temp -intstyle ise -prj G:/Xilinx_Projects/first_project/RSA/RSA_Encryption_stx_beh.prj
Determining compilation order of HDL files
Analyzing Verilog file "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" into library isim_temp
ERROR:HDLCompiler:806 - "GARO.v" Line 11: Syntax error near "begin".
ERROR:HDLCompiler:525 - "GARO.v" Line 14: Inconsistent dimension in declaration
ERROR:HDLCompiler:806 - "GARO.v" Line 14: Syntax error near "}".
ERROR:HDLCompiler:598 - "GARO.v" Line 1: Module <fibonacci_lfsr_nbit> ignored due to previous errors.
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 32: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 57: Syntax error near "=".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 70: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 71: Syntax error near "+".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 75: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 78: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 92: Syntax error near ")".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 93: Syntax error near "i".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 149: Syntax error near ";".
ERROR:HDLCompiler:806 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 154: Syntax error near "begin".
ERROR:HDLCompiler:53 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: <RST_N> is not a port.
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 230: d is an unknown type
ERROR:HDLCompiler:1059 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 232: received is an unknown type
ERROR:HDLCompiler:598 - "G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v" Line 4: Module <RSA_Encryption> ignored due to previous errors.
Verilog file G:/Xilinx_Projects/first_project/RSA/RSA_Encryption.v ignored due to errors
Process "Behavioral Check Syntax" failed
Process "Behavioral Check Syntax" failed
答案 0 :(得分：3)
这里有很多错误。
但最重要的问题是，您正在尝试编写Verilog代码，就好像它是一种过程编程语言一样。这不起作用; Verilog是一种硬件描述语言。您不能使用declare -a MY_ARRAY=(
$( eval "{ printf %.2s 0_{1..$((From-1))};
printf %.2s 1_{$From..$To};
printf %.2s 0_{$((To+1))..100}; }" |
tr _ ' '
)
)
和for循环等构造来实现硬件迭代;这些操作必须以时钟逻辑的形式实现。
获得有关FPGA设计的优秀教科书并通过它完成工作。你需要学习很多东西。
如果这是课程作业：请联系您的教授或助教现在。你不会在截止日期前完成。