我正在做ROM并且代码完全合成并且工作正常,但显示出严重警告,当我运行实现它显示" [放置30-494]设计是空的"我查看了xillinx网站,但没有解决此错误的方法。我会在这里展示我的代码,希望你们帮助我:
`timescale 1ns / 1ps
module ROM(output [7:0] LED, [4:0] Ao, input [7:0] D, [4:0] A, Clear, Load);
reg [7:0] Store [0:31];
initial
begin
Store[0]<=4'b00000000;
Store[1]<=4'b00000000;
Store[2]<=4'b00000000;
Store[3]<=4'b00000000;
Store[4]<=4'b00000000;
Store[5]<=4'b00000000;
Store[6]<=4'b00000000;
Store[7]<=4'b00000000;
Store[8]<=4'b00000000;
Store[9]<=4'b00000000;
Store[10]<=4'b00000000;
Store[11]<=4'b00000000;
Store[12]<=4'b00000000;
Store[13]<=4'b00000000;
Store[14]<=4'b00000000;
Store[15]<=4'b00000000;
Store[16]<=4'b00000000;
Store[17]<=4'b00000000;
Store[18]<=4'b00000000;
Store[19]<=4'b00000000;
Store[20]<=4'b00000000;
Store[21]<=4'b00000000;
Store[22]<=4'b00000000;
Store[23]<=4'b00000000;
Store[24]<=4'b00000000;
Store[25]<=4'b00000000;
Store[26]<=4'b00000000;
Store[27]<=4'b00000000;
Store[28]<=4'b00000000;
Store[29]<=4'b00000000;
Store[30]<=4'b00000000;
Store[31]<=4'b00000000;
end
always @(*)
begin
if(Load)
if (D[7:0])
begin
Store[0]<= LED;
Store[1]<= LED;
Store[2]<= LED;
Store[3]<= LED;
Store[4]<= LED;
Store[5]<= LED;
Store[6]<= LED;
Store[7]<= LED;
Store[8]<= LED;
Store[9]<= LED;
Store[10]<= LED;
Store[11]<= LED;
Store[12]<= LED;
Store[13]<= LED;
Store[14]<= LED;
Store[15]<= LED;
Store[16]<= LED;
Store[17]<= LED;
Store[18]<= LED;
Store[19]<= LED;
Store[20]<= LED;
Store[21]<= LED;
Store[22]<= LED;
Store[23]<= LED;
Store[24]<= LED;
Store[25]<= LED;
Store[26]<= LED;
Store[27]<= LED;
Store[28]<= LED;
Store[29]<= LED;
Store[30]<= LED;
Store[31]<= LED;
end
else if(A[4:0])
begin
Store[0]<= Ao;
Store[1]<= Ao;
Store[2]<= Ao;
Store[3]<= Ao;
Store[4]<= Ao;
Store[5]<= Ao;
Store[6]<= Ao;
Store[7]<= Ao;
Store[8]<= Ao;
Store[9]<= Ao;
Store[10]<= Ao;
Store[11]<= Ao;
Store[12]<= Ao;
Store[13]<= Ao;
Store[14]<= Ao;
Store[15]<= Ao;
Store[16]<= Ao;
Store[17]<= Ao;
Store[18]<= Ao;
Store[19]<= Ao;
Store[20]<= Ao;
Store[21]<= Ao;
Store[22]<= Ao;
Store[23]<= Ao;
Store[24]<= Ao;
Store[25]<= Ao;
Store[26]<= Ao;
Store[27]<= Ao;
Store[28]<= Ao;
Store[29]<= Ao;
Store[30]<= Ao;
Store[31]<= Ao;
end
else if (Clear)
begin
Store[0]<=4'b00000000;
Store[1]<=4'b00000000;
Store[2]<=4'b00000000;
Store[3]<=4'b00000000;
Store[4]<=4'b00000000;
Store[5]<=4'b00000000;
Store[6]<=4'b00000000;
Store[7]<=4'b00000000;
Store[8]<=4'b00000000;
Store[9]<=4'b00000000;
Store[10]<=4'b00000000;
Store[11]<=4'b00000000;
Store[12]<=4'b00000000;
Store[13]<=4'b00000000;
Store[14]<=4'b00000000;
Store[15]<=4'b00000000;
Store[16]<=4'b00000000;
Store[17]<=4'b00000000;
Store[18]<=4'b00000000;
Store[19]<=4'b00000000;
Store[20]<=4'b00000000;
Store[21]<=4'b00000000;
Store[22]<=4'b00000000;
Store[23]<=4'b00000000;
Store[24]<=4'b00000000;
Store[25]<=4'b00000000;
Store[26]<=4'b00000000;
Store[27]<=4'b00000000;
Store[28]<=4'b00000000;
Store[29]<=4'b00000000;
Store[30]<=4'b00000000;
Store[31]<=4'b00000000;
end
end
endmodule
&#13;
严重警告是
[Common 17-69]命令失败:无法将站点分配给多个端口
答案 0 :(得分:1)
您的输出(LED和Ao)似乎在您的代码中用作输入:
...
Store[15]<= LED;
...
Store[7]<= Ao;
...
它应该是:
...
LED <= Store[15];
...
Ao <= Store[7];
...
如果您的输出从未被驱动,则该工具将不会同时使用模块和信号。
答案 1 :(得分:0)
在我总是阻止之前对赋值进行了一些更改后,我改变了整个始终阻止:
这是我做的,感谢@grorel:
`timescale 1ns / 1ps
module ROM(output [7:0] LED, [4:0] Ao, input [7:0] D, [4:0] A, input Clear, input Load);
reg [7:0] Store [0:31];
assign Ao = A;
assign LED = Store[A];
initial
begin
Store[0]<=8'b00000000;
Store[1]<=8'b00000000;
Store[2]<=8'b00000000;
Store[3]<=8'b00000000;
Store[4]<=8'b00000000;
Store[5]<=8'b00000000;
Store[6]<=8'b00000000;
Store[7]<=8'b00000000;
Store[8]<=8'b00000000;
Store[9]<=8'b00000000;
Store[10]<=8'b00000000;
Store[11]<=8'b00000000;
Store[12]<=8'b00000000;
Store[13]<=8'b00000000;
Store[14]<=8'b00000000;
Store[15]<=8'b00000000;
Store[16]<=8'b00000000;
Store[17]<=8'b00000000;
Store[18]<=8'b00000000;
Store[19]<=8'b00000000;
Store[20]<=8'b00000000;
Store[21]<=8'b00000000;
Store[22]<=8'b00000000;
Store[23]<=8'b00000000;
Store[24]<=8'b00000000;
Store[25]<=8'b00000000;
Store[26]<=8'b00000000;
Store[27]<=8'b00000000;
Store[28]<=8'b00000000;
Store[29]<=8'b00000000;
Store[30]<=8'b00000000;
Store[31]<=8'b00000000;
end
always @(*)
begin
if (Load)
begin
Store[A]<= D;
end
else if (Clear)
begin
Store[A]<= 8'b00000000;
end
end
endmodule
&#13;
初始应该是8位而不是4位