Question

为了练习，我尝试制作VHDL代码来运行Rotary encoder硬件。它充满了去抖，正交解码器和向上/向下计数器代码。

不幸的是，当使用测试平台运行模拟时，我的结果令人失望，所以我决定需要分别对每个块进行分析。对于去抖动代码，我创建了一个符号文件并生成了下面的电路

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在尝试在模拟中去除测试台信号时，我发现我的结果非常糟糕，所以我相信我错过了一些东西。

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编码器块的VHDL代码可以在这里找到：

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY debounce_a IS
GENERIC( counter_size  :  INTEGER := 8); --counter size (8 bits gives 51.6 us with 5MHz clock)
PORT(
clk     : IN  STD_LOGIC;  --input clock
bounce_a  : IN  STD_LOGIC;  --input signal to be debounced
result  : OUT STD_LOGIC); --debounced signal
END debounce_a;

ARCHITECTURE logic OF debounce_a IS
SIGNAL flipflops   : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC;                    --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN

counter_set <= flipflops(0) xor flipflops(1);   --determine when to start/reset counter

PROCESS(clk) -- occurs within a clock event
BEGIN
IF(clk'EVENT and clk = '1') THEN -- can be rising_edge(clk)
flipflops(0) <= bounce_a;                   -- adresses the signal as a set value
  flipflops(1) <= flipflops(0);
  If(counter_set = '1') THEN                  --reset counter because input is changing
    counter_out <= (OTHERS => '0');           --set all bits to '0'
  ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
    counter_out <= counter_out + 1;
  ELSE                                        --stable input time is met
    result <= flipflops(1);
  END IF;    
END IF;
END PROCESS;
END logic;

它可能充满了不必要的逻辑，因为我对我正在做的事情有一个有限的想法，我带了一个朋友一般的去抖代码并编辑它以尝试并满足我的特定需求。

如果需要额外的东西，我愿意提供。我觉得这是一个非常基本的错误，但我只需要任何帮助。

以下是我使用的测试平台代码，如果它有助于识别切换属性：

   LIBRARY ieee;                                               
   USE ieee.std_logic_1164.all;                                

   ENTITY decodeblock_vhd_tst IS
   END decodeblock_vhd_tst;
   ARCHITECTURE decodeblock_arch OF decodeblock_vhd_tst IS
   -- constants   
   CONSTANT clk_period : TIME := 20 ns;
   CONSTANT num_clk_cycles : INTEGER := 100;                                              
   -- signals                                                   
     SIGNAL b_Input : STD_LOGIC;
     SIGNAL b_output : STD_LOGIC;
     SIGNAL CLOCK_50 : STD_LOGIC := '0'; 
     COMPONENT decodeblock
 PORT (
 b_Input : IN STD_LOGIC;
 b_output : OUT STD_LOGIC;
 CLOCK_50 : IN STD_LOGIC
 );
     END COMPONENT;
     BEGIN
i1 : decodeblock
PORT MAP (
    -- list connections between master ports and signals
b_Input => b_Input,
b_output => b_output,
CLOCK_50 => CLOCK_50
);
    init : PROCESS                                               
    -- variable declarations                                     
    BEGIN  
    b_input <= '0',
       '1' after 1.1 ns,
       '0' after 2.9 ns,                                                     
       '1' after 5.1 ns,
       '0' after 7.6 ns, 
       '1' after 9.9 ns, 
       '0' after 12.5 ns, 
       '1' after 15.4 ns, 
       '0' after 18.6 ns, 
       '1' after 22.1 ns, 
       '0' after 25.9 ns, 
       '1' after 29.7 ns, 
       '0' after 33.8 ns, 
       '1' after 38.2 ns;

        -- variable declarations                                                                                            
        for i in 1 to num_clk_cycles loop
        CLOCK_50 <= not CLOCK_50;          
        wait for clk_period/2; 
        CLOCK_50 <= not CLOCK_50;     
        wait for clk_period/2;      
        end loop;                       
        WAIT;                                                    
        END PROCESS init;                                          
        always : PROCESS                                              
        -- optional sensitivity list                                  
        -- (        )                                                 
        -- variable declarations                                      
        BEGIN                                                         
    -- code executes for every event on sensitivity list  
        WAIT;                                                        
        END PROCESS always;                                          
        END decodeblock_arch;

编码器Debounce VHDL

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