Question

我正在为FPGA上的声音合成器工作延迟单元，但是当尝试在Modelsim中编译以模拟我时会收到以下错误：＆＃34;子程序TO_SIGNED＆＃34;没有可行的条目。图书馆IEEE; 使用IEEE.STD_LOGIC_1164.ALL; 使用IEEE.NUMERIC_STD.ALL;

ENTITY Delay IS
    -- Delay time in ms
PORT(
    Sample  : in STD_LOGIC_VECTOR(11 DOWNTO 0);
    Delay   : in INTEGER RANGE 0 to 2000;               -- Echo Delay in ms, <2s
    Gain    : in INTEGER Range 0 to 7;              -- Gain of the Echo, 0/8 to 7/8
    clk     : in STD_LOGIC;
    Reset   : in STD_LOGIC;

    Output  : Out STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END Delay;

ARCHITECTURE Delay_Arch OF Delay IS 
    BEGIN
DelayOffset <= Delay*40;                                              -- Number of steps back in the buffer for x ms delay
Process(clk)
BEGIN
IF (Reset = '1') THEN                                                 -- Standard Reset
    CircBuffer <= (OTHERS=>(OTHERS=>'0'));
    Counter <= 0;
ELSIF RISING_EDGE(clk) THEN
    CircBuffer(Counter) <= Sample;                                    -- Save Data in to circBuffer

    IF (DelayOffset > Counter) THEN                                   -- Wrap around for counter
        OutBuff(11 DOWNTO 0) <= CircBuffer(79999-(DelayOffset-Counter));
    ELSE
        OutBuff(11 DOWNTO 0) <= CircBuffer(Counter-DelayOffset);                      -- Load sound from previous Sample (Delay)
    END IF;
    OutBuffInt <= (To_integer(Signed(OutBuff)) * Gain);                   -- Multiply with gain
    Outvect <= To_signed(OutBuffInt, Outvect'length);  <----- ERROR
    Output <= Outvect(14 DOWNTO 3);
    IF (Counter = 79999) THEN 
        Counter <= 0;
    ELSE
    Counter <= Counter + 1;
    END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

我无法在代码中发现任何问题。是否有我缺少的东西，或者只是to_signed无法正常工作？

Answer 1

Morten Zilmer指出，这里存在多个问题。但是为了回答你的问题，“子程序没有可行的条目”错误意味着函数调用的参数和/或目标的类型与任何可用的声明都不匹配。在您的情况下，只有一个名为to_signed的函数可见，在ieee.numeric_std中定义如下：

function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;

您没有包含信号声明，但我猜您的Outvect信号被声明为std_logic_vector而不是signed，因此错误。

使用To_signed VHDL，＆＃34;子程序To_signed＆＃34;

1 个答案: