我一直在为交通灯控制器编写状态机。
-- Ampelsteuerung mit Zähler und FSM Componente
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AMPLSTRG is
port ( CLK, B1, RES : in bit;
MAINRE, MAINYE, MAINGR : out bit;
FARMRE, FARMYE, FARMGR : out bit);
end AMPLSTRG;
architecture FUNKTION of AMPLSTRG is
type AMP_STATE is (S0, S1, S2, S3, S4, S5, S6, S7, S8); -- Typendefinition
signal SCLR : bit;
signal CYCLES : unsigned (4 downto 0);
signal STATE, NEXT_STATE : AMP_STATE; -- STATE = aktueller Status, NEXT_STATE nächster Status (Typenzuweisung)
begin
-- COUNTER Prozess
CO: process (CLK)
begin
if CLK = '1' and CLK'event then
if SCLR = '1' then
CYCLES <= (others => '0'); -- 'others' = gesamten Vektor auf '0' setzten
else
CYCLES <= CYCLES + 1;
end if;
end if;
end process CO;
AMP_SYNC: process (CLK, RES)
begin
if RES = '1' then
STATE <= S0 after 5 ns;
SCLR <= '1' after 5 ns;
elsif CLK = '1' and CLK'event then
STATE <= NEXT_STATE after 5 ns; -- Zustandszuweisung
end if;
end process AMP_SYNC;
AMP_KOMB: process (STATE, B1, CYCLES)
begin
-- default Werte Setzen
MAINRE <= '0' after 5 ns;
MAINYE <= '0' after 5 ns;
MAINGR <= '0' after 5 ns;
FARMRE <= '0' after 5 ns;
FARMYE <= '0' after 5 ns;
FARMGR <= '0' after 5 ns;
NEXT_STATE <= STATE;
SCLR <= '0';
case STATE is
when S0 => if B1 = '1' then
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S1 after 5 ns;
SCLR <= '1' after 5 ns;
else -- MAINGR | FARMRE until B1 pressed
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
SCLR <= '1' after 5 ns;
end if;
when S1 => if CYCLES = '5' then
MAINGR <= '0' after 5 ns;
MAINYE <= '1' after 5 ns;
NEXT_STATE <= S2 after 5 ns;
SCLR <= '1';
else -- MAINGR | FARMRE for 5 sec
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S2 => if CYCLES = '5' then MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S3 after 5 ns;
SCLR <= '1';
else -- MAINYE | FARMRE for 5 sec
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S3 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
NEXT_STATE <= S4 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S4 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
FARMGR <= '1' after 5 ns;
NEXT_STATE <= S5 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE | FARMYE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
end if;
when S5 => if CYCLES = '30' then
MAINRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
NEXT_STATE <= S6 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMGR for 30 sec
MAINRE <= '1' after 5 ns;
FARMGR <= '1' after 5 ns;
end if;
when S6 => if CYCLES = '5' then
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S7 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMYE for 5 sec
MAINRE <= '1' after 5 ns;
FARMYE <= '1' after 5 ns;
end if;
when S7 => if CYCLES = '2' then
MAINRE <= '1' after 5 ns;
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S8 after 5 ns;
SCLR <= '1';
else -- MAINRE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
when S8 => if CYCLES = '2' then
MAINGR <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
NEXT_STATE <= S0 after 5 ns;
SCLR <= '1';
else -- MAINRE | MAINYE | FARMRE for 2 sec
MAINRE <= '1' after 5 ns;
MAINYE <= '1' after 5 ns;
FARMRE <= '1' after 5 ns;
end if;
end process AMP_KOMB;
end FUNKTION;
在 Modelsim PE学生中编译代码时，我收到以下错误：
No feasible entries for infix operator "="
在尝试了许多不同的库之后，我无法找到解决此错误的任何解决方案。我想这是错误的库或错误使用＆＃34; =＆＃34;运营商。
以下是Modelsim的完整错误报告：
** Error: [...]/AMPSTR.vhdl(68): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(68): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(78): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(78): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(87): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(87): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(98): No feasible entries for infix operator "=".
** Error: [...]/AMPSTR.vhdl(98): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
** Error: [...]/AMPSTR.vhdl(109): near "'": syntax error
** Error: [...]/AMPSTR.vhdl(114): near "else": expecting END or WHEN
** Error: [...]/AMPSTR.vhdl(117): near "if": expecting PROCESS
答案 0 :(得分：1)
在if CYCLES = '5' then你期望发生什么？
CYCLES是UNSIGNED。无论是numeric_std.unsigned还是来自其他非标准库的其他类型的UNSIGNED，我都说不出来，但我建议只使用numeric_std库。
'5'是一个字符文字，与5不同，它是一个整数文字。根据错误消息，编译器显然无法在UNSIGNED和字符文字之间找到相等运算符。
在if B1 = '1' then中，'1'可以是字符文字也可以是字面文字;两者都是可见的，但只有一个是有意义的（有一个为它定义的相等运算符）所以编译器对这个表达式没有问题。
答案 1 :(得分：1)
你错过了
end case;
之前
end process AMP_KOMB;
您使用的是错误的数字包，因为您正在使用您应该使用numeric_bit的位类型。你不应该混合使用std_logic_unsigned和numeric_xxx：
library ieee;
-- use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.numeric_std.all;
use ieee.numeric_bit.all;
CYCLES的数组长度为5，索引范围为(4 downto 0)。与它一起使用的可接受的文字应该是位串：
when S1 => if CYCLES = '5' then
应该是：
when S1 => if CYCLES = "00101" then
等。 （评估每个地方的CYCLES）。请注意，'30'不是字符文字，位字符串文字中有30个是"11110"。
修复所有这些以及您的VHDL设计规范分析和阐述。没有编写测试台，我没有模拟它。
在看到Brian的回答之后，值得指出的是，numeric_bit还有一个unsigned的类型声明以及相关的运算符。
答案 2 :(得分：0)
David和Brian之前没有解决一些额外问题：
SCLR有多个驱动程序。只有一个进程应为信号赋值。如果需要，请在这两个过程之间实施“通信协议”。