Question

我的代码是关于使用VHDL和maxplus2的乒乓游戏。我无法理解它。

library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_unsigned.all;
-- use ieee.std_logic_arith.all;

entity center is 
    port ( 
        clk:    in  std_logic;
        ca:     in  std_logic;
        cb:     in  std_logic;
        enable: in  std_logic;
        a:      in  std_logic;
        b:      in  std_logic;
        ball:   out std_logic_vector(16 downto 0);
        sa:     out std_ulogic;
        sb:     out std_ulogic;
        over:   inout std_ulogic
    );
end center;

architecture behavior of center is
    signal direction : integer range 0 to 2; 
    signal num : integer range -1 to 17;  
begin
    process (enable,ca,cb,a,b,clk)
    begin        
        if enable = '0' then   
            over <= '0';
            sa <= '0';
            sb <= '0';
        elsif enable = '1' and rising_edge(clk) then
            if direction = 2 then
                if ca = '1' then
                    direction <= 0;       
                    num <= 1;
                elsif cb = '1' then 
                    direction <= 1;
                    num <= 16;
                else
                    direction <= 2;
                    num <= 8;
                end if;
            elsif direction = 0 and num > 0 then
                if b = '1' then
                    if num < 2 then
                        num <= num - 1;
                        direction <= 1;
                    else
                        direction <= 2;
                        sa <= '1' after 10 ns;
                        sb <= '0' after 10 ns;
                        over <= not over after 10 ns;
                    end if;
                end if;        
            elsif direction = 1 and num <= 16 then
                if a = '1' then
                    if num >= 14 then
                        num <= num + 1;
                        direction <= 2;
                    else
                        direction <= 2;
                        sa <= '0' after 10 ns;
                        sb <= '1' after 10 ns;
                        over <= not over after 10 ns;
                    end if;
                end if;
            elsif direction = 0 and num = -1 then
                num <= 8;
                direction <= 2;
                sa <= '0' after 10 ns;
                sb <= '1' after 10 ns;
                over <= not over after 10 ns;
            elsif direction = 0 and num = -1 then
                num <= 8;
                direction <= 2;
                sa <= '0' after 10 ns;
                sb <= '1' after 10 ns;
                over <= not over after 10 ns;
            end if;
        end if;
    end process;
end architecture behavior;

但是我收到了一个错误：

不支持子程序中的信号参数

我很困惑，我不知道为什么会收到这个错误。

Answer 1

我认为大卫还说你需要提供更多信息。它对我来说是什么样的，你正在编写一个测试平台，上面的代码无法正确合成。 ISE会告诉您，您的语法正常，但忽略延迟IE after关键字。 elsif关键字仅用于模拟。

那说我也会清理代码有很多冗余。 FX
最后两个clk语句。只需要一个。和敏感性清单。只有enable和process (enable,clk) begin if enable = '0' then over <= '0'; sa <= '0'; sb <= '0'; elsif rising_edge(clk) then case( direction ) is when 0 => if num > 0 then if b = '1' then if num < 2 then num <= num - 1; direction <= 1; else direction <= 2; sa <= '1' after 10 ns; sb <= '0' after 10 ns; over <= not over after 10 ns; end if; end if; elsif num = -1 then num <= 8; direction <= 2; sa <= '0' after 10 ns; sb <= '1' after 10 ns; over <= not over after 10 ns; end if; when 1 => if num <= 16 then if a = '1' then if num >= 14 then num <= num + 1; direction <= 2; else direction <= 2; sa <= '0' after 10 ns; sb <= '1' after 10 ns; over <= not over after 10 ns; end if; end if; end if; when 2 => if ca = '1' then direction <= 0; num <= 1; elsif cb = '1' then direction <= 1; num <= 16; else direction <= 2; num <= 8; end if; when others => NULL; end case ; end if; end process;应该在那里。

我试图清理你的代码：

after

尝试删除Area Code Count BP 90-99 10 CL 78-87 10个关键字，看看它是否会编译。

子程序中的信号参数不受支持错误

1 个答案: