Question

我真的很困惑。

我做了verilog编程，并在VCS中编译和执行。它在预期的时钟周期给出正确的值。

当我运行时，它是ivl32，它给出了稍微不同的值。

我完全糊涂了。

有人可以告诉我这个问题是什么吗？

Answer 1

主要的电子设计自动化（EDA）工具供应商各有自己的 SystemVerilog模拟器。这些工具也是由不同的人在不同时间编写的，更具体地说是仿真算法。所以一般来说它们的行为方式相同。

称为 Indeterminacy ，必须注意确保模型或测试平台的编写方式不确定无关紧要。

不确定 ：不确定性

参见LRM示例：

assign b = a;
initial 
begin
  a = 1;
  #1 a = 0;
  $display(b);
end

因为初始化的执行与assign语句交错，所以b的值可以是b'0'或'1'，不同的模拟器给出不同的输出。

<强> Questasim：

-- Compiling module chk

Top level modules:
    chk
Reading pref.tcl

# 10.4

# vsim -lib work chk -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# //  Questa Sim-64
# //  Version 10.4 linux_x86_64 Dec  2 2014
# //
# //  Copyright 1991-2014 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //  THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# //  INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# //  DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# //  FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# //  THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.chk(fast)
# run -all
# ----*---- Value of b is :: 0 ----*----
#  quit -f
# End time: 14:32:20 on May 10,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0

<强> INCISIV：

irun: 12.20-s015: (c) Copyright 1995-2013 Cadence Design Systems, Inc.
Recompiling... reason: file './me.v' is newer than expected.
    expected: Tue May 10 14:31:09 2016
    actual:   Tue May 10 14:33:54 2016
file: me.v
    module worklib.chk:v
        errors: 0, warnings: 0
        Caching library 'worklib' ....... Done
    Elaborating the design hierarchy:
    Top level design units:
        chk
    Building instance overlay tables: .................... Done
    Generating native compiled code:
        worklib.chk:v <0x5f262bc0>
            streams:   1, words:   825
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                    Instances  Unique
        Modules:            1       1
        Registers:          1       1
        Scalar wires:       1       -
        Initial blocks:     1       1
        Cont. assignments:  0       1
    Writing initial simulation snapshot: worklib.chk:v
Loading snapshot worklib.chk:v .................... Done
ncsim> source /sib/tools/Cadence/Install/INCISIV122/tools/inca/files/ncsimrc
ncsim> run
----*---- Value of b is :: 1 ----*----
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

如果您在代码中竞争，那么可能会发生这种问题。

Verilog程序，当我在VCS中编译时获得正确的输出，但是当我在IVL中编译时得到不同的输出

1 个答案: