我的Verilog程序的输出为“ x”,这意味着寄存器中没有存储任何内容,但是我不知道为什么?

时间:2019-03-28 23:46:40

标签: verilog

我正在为分配编写Verilog程序,要求为5位加减法器编写程序。运行该程序后,由于某种原因,我的输出为“ x”,因为我不熟悉Verilog。

module TestMod;   

   parameter STDIN = 32'h8000_0000;                             // I/O address of keyboard input channel

   reg [7:0] str [1:3], str1[1:2];                      
   reg [4:0] X, Y;                                          // 5-bit X, Y to sum
   reg Op;
   wire [4:0] S;                                                // 5-bit Sum to see as result
   wire C4,C5;                                                  // like to know this as well from result of adder

   initial 
   begin

      $display("Enter X (two digit 00~15 since max is 01111): ");
      str[1] = $fgetc(STDIN);
      str[2] = $fgetc(STDIN);
      str[3] = $fgetc(STDIN);
      X = (str[1] - 48)*10 + (str[2] - 48);

      $display("Enter Y (two digit 00~15 since max is 01111): ");
      str[1] = $fgetc(STDIN);
      str[2] = $fgetc(STDIN);
      str[3] = $fgetc(STDIN);
      Y = (str[1] - 48)*10 + (str[2] - 48);

      $display("Enter either '+' or '-': ");
      str1[1] = $fgetc(STDIN);
      str1[2] = $fgetc(STDIN);

      if(str1[1] == 43)
        Op = str1[1] + 5;
      else
        Op = str1[1] + 4;

      #20;                                                      // wait until adder gets them processed

      $display("X = %d (%b)\tY = %d (%b)\tc0 = %d", X,X,Y,Y,Op);
      $display("Result = %d (as unsigned %b)", S, S);
      $display("C4 = %b\tC5 = %b\tE = %b",C4,C5,C4^C5);

      if(C4^C5 == 0'b0)
        $display("Since E is 0, C5 is not needed");
      else  
        $display("Since E is 1, correct with C5 in front: %b%b", C4^C5, S);

   end

   BigAdder BA(X,Y,Op,S,C4,C5);

endmodule

module BigAdder(X, Y, Op, S, C4, C);

    input [4:0] X, Y;
    input Op;
    output [4:0] S;                                             // S should be similar
    output C4,C;                                                // another output for a different size
    wire C1,C2,C0,C3,C5,Y1,Y2,Y3,Y4;        

    xor(Y1, Y[0], Op);
    xor(Y2, Y[1], Op);
    xor(Y3, Y[2], Op);
    xor(Y4, Y[3], Op);
    xor(C, C5, Op);

    FullAdderMod a0(X[0], Y1, Op, S[0], C0);
    FullAdderMod a1(X[1], Y2, C0, S[1], C1);
    FullAdderMod a2(X[2], Y3, C1, S[2], C2);
    FullAdderMod a3(X[3], Y4, C2, S[3], C3);
    FullAdderMod a4(X[4], Y5, C3, S[4], C5);

endmodule

module FullAdderMod(X, Y, Cin, S, Cout);                        // single-bit adder module

    input X,Y,Cin;
    output Cout,S;

    assign S = X ^ Y ^ Cin;
    assign Cout = (X & Cin) | (X & Y) | (Y & Cin);

endmodule

在我的作业中,我必须按照教授的说明显示输出,如下所示:

 atoz[35]% demo-a.out
   Enter X (range 00 ~ 15): 
   01
   Enter Y (range 00 ~ 15): 
   15
   Enter either '+' or '-': 
   -
   X=00001 ( 1) Y=01111 (15) C0=1
   Result=10010 (as unsigned 18)
   C4=0 C5=0 E=0
   Since E is 0, C5 is not needed.

   atoz[36]% demo-a.out
   Enter X (range 00 ~ 15): 
   11
   Enter either Y (range 00 ~ 15): 
   15
   Enter either '+' or '-': 
   +
   X=01011 (11) Y=01111 (15) C0=0
   Result=11010 (as unsigned 26)
   C4=1 C5=0 E=1
   Since E is 1, correct with C5 in front: 011010

但是我的实际输出是:

ent_3$ ./a.out
Enter X (two digit 00~15 since max is 01111):
12
Enter Y (two digit 00~15 since max is 01111):
13
Enter either '+' or '-':
+
X = 12 (01100)  Y = 13 (01101)  c0 = 0
Result =  X (as unsigned x1001)
C4 = z  C5 = x  E = x
Since E is 1, correct with C5 in front: xx1001

任何人都可以帮助我吗?

0 个答案:

没有答案