Question

我正在为我的大学项目altera板上的数字时钟工作。我面临的问题是我的时间是29而不是24！我使用整数类型为我的小时数字0到9;我得到if声明，当我的小时数字是2和小时右数字是3我想要我的第二，分钟和小时00:00:00 ..但它没有实现为什么？需要一些建议......谢谢你这是我的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity master is 

 port( 
 clk : in std_logic;
 hrs_lft : out std_logic_vector(1 downto 0 );
 hrs_rght : out std_logic_vector(3 downto 0 );
 min_lft : out std_logic_vector(2 downto 0 );
 min_rght : out std_logic_vector(3 downto 0 );
 second_lft: out std_logic_vector(2 downto 0);
 second_rght : out std_logic_vector( 3 downto 0)
 );
 end master;


 architecture bhv of master is
 signal second_lft_int : integer range 0 to 5;
 signal second_rght_int : integer range 0 to 9;
 signal min_lft_int : integer range 0 to 5;
 signal min_rght_int : integer range 0 to 9;
 signal hrs_lft_int : integer range 0 to 2;
 signal hrs_rght_int : integer range 0 to 9;
 begin 
 process(clk)
 begin 
 if (rising_edge(clk)) then
 second_rght_int <= second_rght_int + 1;
 if second_rght_int = 9 then 

 second_lft_int <= second_lft_int + 1;
 second_rght_int <= 0; 
   if second_lft_int  = 5 then 
       second_lft_int <= 0;   

        min_rght_int <= min_rght_int + 1;

            if min_rght_int = 9 then
              min_lft_int <= min_lft_int + 1;
              min_rght_int <= 0;
          if min_rght_int = 5 then
                  hrs_rght_int <= hrs_rght_int + 1;
                    min_rght_int <= 0;
               if  hrs_rght_int = 9 then
                  hrs_lft_int <= hrs_lft_int + 1;
                  if (hrs_rght_int = 3 and hrs_lft_int = 2) then
                  hrs_lft_int <= 0;
                  hrs_rght_int <= 0;
              min_lft_int <= 0;
              min_rght_int <= 0;  
     second_rght_int <= 0;
     second_lft_int <= 0;
     end if ;
     end if;
     end if;
     end if;
     end if;
     end if;
     end if;
     end process;
     second_rght<=                          std_logic_vector(to_unsigned(second_rght_int,second_rght'length));
    second_lft<=std_logic_vector(to_unsigned(second_lft_int,second_lft'length));
    min_rght<= std_logic_vector(to_unsigned(min_rght_int,min_rght 'length));
    min_lft <= std_logic_vector(to_unsigned(min_lft_int,min_lft'length));
    hrs_rght<= std_logic_vector(to_unsigned(hrs_rght_int,hrs_rght 'length));
    hrs_lft <= std_logic_vector(to_unsigned(hrs_lft_int,hrs_lft'length));
end bhv;

Answer 1

你的过程看起来不对，所以我从头开始写了这个：

    process (clk)
    begin 
        if rising_edge(clk) then
            if second_rght_int = 9 then
                second_rght_int <= 0;
                if second_lft_int = 5 then
                    second_lft_int <= 0;
                    if min_rght_int = 9 then
                        min_rght_int <= 0;
                        if  min_lft_int = 5 then
                             min_lft_int <= 0;
                            if (hrs_lft_int = 2 and hrs_rght_int = 4)
                                             or hrs_rght_int = 9 then
                                hrs_rght_int <= 0;
                                    if hrs_lft_int = 2 then
                                        hrs_lft_int <= 0;
                                    else
                                        hrs_lft_int <= hrs_lft_int + 1;
                                    end if;
                            else 
                                hrs_rght_int  <= hrs_rght_int + 1;
                            end if;
                        else 
                             min_lft_int <=  min_lft_int + 1;
                        end if;
                    else
                        min_rght_int <= min_rght_int + 1;
                    end if;
                else 
                    second_lft_int <= second_lft_int + 1;
                end if;
            else
                second_rght_int <= second_rght_int + 1;
            end if;
        end if;
    end process;

这就是：

在VHDL中，“+”表示整数被定义为对类型整数而不是模块整数的操作，您必须自己检查边界条件。

您可能还会注意到我在模拟中将clk率设置为1 ps。有点过分，但我想搜索翻滚事件。

测试平台可以包含与clk的单个端口关联的直接实体实例化一样少的内容。（波形来自被测设备）。

需要有关我的vhdl代码的建议

1 个答案: