library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,MCM3);
dff2 : DFF port map(Q2,Clk,add_out1);
dff3 : DFF port map(Q3,Clk,add_out2);
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out3;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(`
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
process(Clk)
begin
if ( rising_edge(Clk) ) then
qt <= D;
end if;
end process;
end Behavioral;
当我运行此代码时，它会成功编译无错语法，但我收到了一些警告，因此我没有得到理想的结果。我得到辛，克里金＆amp; Yout在模拟结果中未定义。我尝试过不同的方式，但仍然没有解决这些警告：
1）警告：Xst：1293 - FF / Latch的常数值为0 in 块。优化期间将修剪此FF / Latch 过程
2）警告：Xst：1293 - FF / Latch的常数值为 块中0。这个FF / Latch将在期间进行修剪 优化过程。
3）警告：Xst：1293 - FF / Latch有一个 块中的常量值为0。这个FF / Latch将被修剪 在优化过程中。
4）警告：Xst：1896 - 由于其他原因 FF / Latch微调，FF / Latch的常数值为0 in 块。
期间将修剪此FF / Latch
答案 0 :(得分：0)
代码似乎没有问题。我认为唯一可能出错的事情是fir模块没有任何重置。 fir的代码如下：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_123 is
port( Clk : in std_logic; --clock signal
reset: in std_logic;
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_123;
architecture Behavioral of fir_123 is
component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal yout_int : signed(15 downto 0);
begin
--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,reset,MCM3);
dff2 : DFF port map(Q2,Clk,reset,add_out1);
dff3 : DFF port map(Q3,Clk,reset,add_out2);
--an output produced at every positive edge of clock cycle.
registered_yout: process
begin
wait until rising_edge(clk);
if (reset = '1') then
yout_int <= (others => '0');
else
yout_int <= add_out3;
end if;
end process;
Yout <= yout_int;
end Behavioral;
我还在dff的reset中添加了，更改的文件如下所示：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dff is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
reset: in std_logic;
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end dff;
architecture Behavioral of dff is
signal qt : signed(15 downto 0) := (others => '0');
begin
Q <= qt;
registered_qt : process
begin
wait until rising_edge(clk);
if (reset = '1') then
qt <= (others => '0');
else
qt <= D;
end if;
end process;
end Behavioral;
我使用的测试平台如下：
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity tb is
end entity tb;
architecture test_bench of tb is
component fir_123 is
port( Clk : in std_logic;
reset : in std_logic;
Xin : in signed(7 downto 0);
Yout : out signed(15 downto 0)
);
end component fir_123;
constant clk_per : time := 8 ns;
signal clk: std_logic;
signal reset: std_logic;
signal Xin : signed(7 downto 0);
signal Yout : signed(15 downto 0);
begin
dft : component fir_123
port map (
Clk => clk,
reset => reset,
Xin => Xin,
Yout => Yout
);
Clk_generate : process --Process to generate the clk
begin
clk <= '0';
wait for clk_per/2;
clk <= '1';
wait for clk_per/2;
end process;
Rst_generate : process --Process to generate the reset in the beginning
begin
reset <= '1';
wait until rising_edge(clk);
reset <= '0';
wait;
end process;
Test: process
begin
Xin <= (others => '0');
wait until rising_edge(clk);
Xin <= (others => '1');
wait until rising_edge(clk);
Xin <= (others => '0');
wait for clk_per*10;
report "testbench finished" severity failure;
end process test;
end architecture test_bench;
我已经在模拟器中检查了波形，并且在重置被解除置位后它们似乎都被定义了。 Xin和Clk未定义的事实表明测试平台有问题。