我有一个用于对内存中的一组数据进行排序的代码。我想合成这段代码，但我有几个问题。我的代码只有一个时钟控制每个块，包括内存。但是，我想知道是否需要在整个合成代码和内存中映射时钟，或者仅在其中一个中映射时钟。我尝试了不同的案例，但没有得到正确答案。 这是我的代码：
module sort_top(
input Go,
input Rst,
input Clk,
input [5:0] N,
output wire [7:0] ReadData,
output reg [4:0] Address,
output reg [7:0] WriteData,
output reg MemWrite,
output reg MemRead
);
DataMemory Only_Mem(Address, WriteData, Clk, MemWrite, MemRead, ReadData);
parameter S_Wait = 0 , S_Initial_C = 1, S_Check_C = 2, S_Initial_D = 3, S_Read_1 = 4, S_Write_1 = 5, S_Read_2 = 6, S_Write_2 =7, S_Swich_1 = 8, S_Swich_2 = 9, S_Update_D = 10, S_Check_D = 11, S_Update_C =12, S_Decision =13;
reg [3:0] State;
reg [5:0] C;
reg signed [4:0]D;
reg [7:0] T1,T2;
always @(posedge Clk)begin
if (Rst ==1) begin
State <= S_Wait;
C <= 5'b00000;
D <= 5'b00000;
T1 <= 8'h00;
T2 <= 8'h00;
end
else begin
case (State)
S_Wait : begin
if (Go == 0)
State <= S_Wait;
else if (Go==1)
State <= S_Initial_C;
end
S_Initial_C : begin
C <= 6'b000001;
State <= S_Check_C;
end
S_Check_C : begin
//Address <=5'bzzzzz ;
if (C == N)
State <= S_Wait;
else if (C != 6'b100000)
State <= S_Initial_D;
end
S_Initial_D : begin
// Address <=5'bzzzzz ;
D <= C;
State <= S_Read_1;
end
S_Read_1 : begin
Address <= D;
MemRead <= 1;
MemWrite <= 0;
State <= S_Write_1;
end
S_Write_1: begin
T1 <= ReadData;
State <= S_Read_2;
end
S_Read_2 : begin
Address <= D-1;
MemRead <= 1;
MemWrite <= 0;
State <= S_Write_2;
end
S_Write_2 : begin
T2 <= ReadData;
Address <= D-1;
MemRead <= 1;
MemWrite <= 0;
State <= S_Decision;
end
S_Decision: begin
if (T2>T1)
State <= S_Swich_1;
else
State <= S_Update_C;
end
S_Swich_1 : begin
WriteData<=T2;
Address <=D ;
MemWrite <= 1;
MemRead <= 0;
State <= S_Swich_2;
end
S_Swich_2 : begin
WriteData <= T1 ;
Address <=D-1 ;
MemWrite <= 1;
MemRead <= 0;
State <= S_Update_D;
end
S_Update_D: begin
//Address <= 5'bzzzzz;
MemWrite <= 0;
MemRead <= 0;
D <= D-1;
State <= S_Check_D;
end
S_Check_D : begin
if (D==5'b00000)
State <= S_Update_C;
else
State <= S_Read_1;
end
S_Update_C : begin
// Address <=5'bzzzzz ;
C <= C+1;
MemWrite <= 0;
MemRead <= 0;
State <= S_Check_C;
end
endcase
end
end
endmodule
这是我尝试合成此代码的XDC文件：
set_property PACKAGE_PIN U9 [get_ports {Go}]
set_property IOSTANDARD LVCMOS33 [get_ports {Go}]
set_property PACKAGE_PIN E3 [get_ports Clk]
set_property IOSTANDARD LVCMOS33 [get_ports Clk]
create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk]
set_property PACKAGE_PIN C12 [get_ports Rst]
set_property IOSTANDARD LVCMOS33 [get_ports Rst]
set_property PACKAGE_PIN R7 [get_ports {N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[0]}]
set_property PACKAGE_PIN R6 [get_ports {N[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[1]}]
set_property PACKAGE_PIN R5 [get_ports {N[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[2]}]
set_property PACKAGE_PIN V7 [get_ports {N[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[3]}]
set_property PACKAGE_PIN V6 [get_ports {N[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[4]}]
set_property PACKAGE_PIN V5 [get_ports {N[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {N[5]}]
##Cellular RAM
##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
set_property PACKAGE_PIN T15 [get_ports Clk]
set_property IOSTANDARD LVCMOS33 [get_ports Clk]
set_property PACKAGE_PIN R12 [get_ports {ReadData[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[0]}]
set_property PACKAGE_PIN T11 [get_ports {ReadData[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[1]}]
set_property PACKAGE_PIN U12 [get_ports {ReadData[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[2]}]
set_property PACKAGE_PIN R13 [get_ports {ReadData[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[3]}]
set_property PACKAGE_PIN U18 [get_ports {ReadData[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[4]}]
set_property PACKAGE_PIN R17 [get_ports {ReadData[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[5]}]
set_property PACKAGE_PIN T18 [get_ports {ReadData[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[6]}]
set_property PACKAGE_PIN R18 [get_ports {ReadData[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ReadData[7]}]
set_property PACKAGE_PIN J18 [get_ports {Address[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Address[0]}]
set_property PACKAGE_PIN H17 [get_ports {Address[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Address[1]}]
set_property PACKAGE_PIN H15 [get_ports {Address[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Address[2]}]
set_property PACKAGE_PIN J17 [get_ports {Address[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Address[3]}]
set_property PACKAGE_PIN H16 [get_ports {Address[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Address[4]}]
set_property PACKAGE_PIN F18 [get_ports {WriteData[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[0]}]
set_property PACKAGE_PIN G18 [get_ports {WriteData[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[1]}]
set_property PACKAGE_PIN G17 [get_ports {WriteData[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[2]}]
set_property PACKAGE_PIN M18 [get_ports {WriteData[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[3]}]
set_property PACKAGE_PIN M17 [get_ports {WriteData[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[4]}]
set_property PACKAGE_PIN P18 [get_ports {WriteData[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[5]}]
set_property PACKAGE_PIN N17 [get_ports {WriteData[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[6]}]
set_property PACKAGE_PIN P17 [get_ports {WriteData[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {WriteData[7]}]
set_property PACKAGE_PIN R11 [get_ports MemWrite]
set_property IOSTANDARD LVCMOS33 [get_ports MemWrite]
set_property PACKAGE_PIN H14 [get_ports MemRead]
set_property IOSTANDARD LVCMOS33 [get_ports MemRead]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
你能帮我解决这个问题吗？
答案 0 :(得分：1)
我认为你的问题是你试图将Clk端口路由到两个不同的FPGA引脚，这是不允许的，特别是因为Clk是一个输入。
现在我不能从你的描述中确定内存是外部设备还是FPGA上的内存。
如果是在FPGA上，则不应为其端口声明FPGA引脚。
如果它是外部的，那么内存模型应该在测试平台中实例化，而不是在芯片设计的顶层。在这种情况下，您可能需要将时钟输入转发到单独的时钟输出以驱动存储器IC时钟，假设这是您将其连接到PCB上的方式。