Question

我使用Verilog实现了一个4x16解码器以及它的测试。对于每种情况，解码器应输出一个16位数字，其中只有一位高。当我运行程序时，我无法获得所有期望的输出。以下是解码器和测试的代码，以及控制台的输出：

4x16解码器：

module Decoder4x16 (input [3:0] select, input enable, output reg [16:0] out);

always @(select, enable)
begin

    if(enable == 1'b0)
        out = 16'b0000000000000000;
    else if(enable == 1'b1)
        if(select == 4'b0000)
            out <= 16'b0000000000000001;
        else if(select == 4'b0001)
            out <= 16'b0000000000000010;
        else if(select == 4'b0010)
            out <= 16'b0000000000000100;
        else if(select == 4'b0011)
            out <= 16'b0000000000001000;
        else if(select == 4'b0100)
            out <= 16'b0000000000010000;
        else if(select == 4'b0101)
            out <= 16'b0000000000100000;
        else if(select == 4'b0110)
            out <= 16'b0000000001000000;
        else if(select == 4'b0111)
            out <= 16'b0000000010000000;
        else if(select == 4'b1000)
            out <= 16'b0000000100000000;
        else if(select == 4'b1001)
            out <= 16'b0000001000000000;
        else if(select == 4'b1010)
            out <= 16'b0000010000000000;
        else if(select == 4'b1011)
            out <= 16'b0000100000000000;
        else if(select == 4'b1100)
            out <= 16'b0001000000000000;
        else if(select == 4'b1101)
            out <= 16'b0010000000000000;
        else if(select == 4'b111)
            out <= 16'b0100000000000000;
        else if(select == 4'b1111)
            out <= 16'b1000000000000000;
    end

endmodule

测试：

module Decoder4x16_test;

reg [3:0] select;
reg enable;
wire [16:0] out;

parameter sim_time = 2800;

Decoder4x16 decoder(select, enable, out);
initial #sim_time $finish;
initial
begin
    select = 4'b0000;
    enable = 1'b0;

    repeat(16) #10 begin
        enable = 1'b1;
        #85 $display("select = %b \t out = %b", select, out);
        select = select + 4'b0001;
    end
end
endmodule

当我运行程序时，它输出正确的输出，直到它到达输入为1101的测试用例。之后，解码器输出错误的值，它应该显示。这是输出：

select = 0000    out = 00000000000000001
select = 0001    out = 00000000000000010
select = 0010    out = 00000000000000100
select = 0011    out = 00000000000001000
select = 0100    out = 00000000000010000
select = 0101    out = 00000000000100000
select = 0110    out = 00000000001000000
select = 0111    out = 00000000010000000
select = 1000    out = 00000000100000000
select = 1001    out = 00000001000000000
select = 1010    out = 00000010000000000
select = 1011    out = 00000100000000000
select = 1100    out = 00001000000000000
select = 1101    out = 00010000000000000
select = 1110    out = 00010000000000000
select = 1111    out = 01000000000000000

Answer 1

此处，out是reg，表示拥有分配给它的值。 else if没有select=4'b1110条件。因此，out 持有或保留其来自select=4'b1101的以前的值。也就是说，out保存显示的值00010000000000000。

因此，为else if添加 select=4'b1110条件，代码正常。

  else if(select == 4'b1110)
            out <= 16'b0100000000000000;

此外，解码器纯粹的组合电路。在创建任何组合逻辑时，首选使用阻止分配（=）。因此，请使用以下语法。

  else if(select == 4'b1110)
            out = 16'b0100000000000000; // blocking

还有一件事要详细说明，请使用always@(*)代替手动敏感度列表。这有助于减少敏感性列表的混淆。

Answer 2

试试这个简单的代码，

module Decoder4x16 (input [3:0] select, 
                    input enable, 
                    output wire [16:0] out);

assign out = {17{enable}} & (1'b1 << select);

endmodule

也在ISE中合成。

Verilog 4x16解码器输出错误的数据

2 个答案: