verilog-用于16位CPU的解码器模块

Question

我已经为解码器模块制作了一个代码，但是当我合成它时会显示一个红色十字标记，表明合成是不成功的。但是，我没有收到任何错误。任何人都可以告诉代码有什么问题吗？

module decode(decode26,PC21,ir235,rd23,rd2345,temp214,fetch2136,PCselect2136);
input wire [31:0]decode26;
input wire [15:0]PC21;
output reg [15:0]ir235; 
output reg [15:0] rd2345,rd23;
output reg [15:0]temp214;
output reg [31:0]fetch2136;
output reg [1:0]PCselect2136;
reg [2:0] wd,rs1,rs2;
reg [7:0] InstMem[65535:0];
reg [15:0] register [7:0];

initial
begin

fetch2136=0;

InstMem[0] = 8'b01000010;                                    //LSB
InstMem[1] = 8'b00100000;                                    //MSB
InstMem[2] = 8'b00000000;                                    //LSB 
InstMem[3] = 8'b00000000;                                    //MSB
InstMem[4] = 8'b00000000;                                    //LSB
InstMem[5] = 8'b00000000;                                    //MSB
InstMem[6] = 8'b00000000;                                    //LSB
InstMem[7] = 8'b00000000;                                    //MSB
InstMem[8] = 8'b00000000;                                    //LSB 
InstMem[9] = 8'b00000000;                                    //MSB
InstMem[10] = 8'b00000000;                                   //LSB
InstMem[11] = 8'b00000000;                                   //MSB
InstMem[12] = 8'b00000000;                                   //LSB
InstMem[13] = 8'b00000000;                                   //MSB 
InstMem[14] = 8'b00000000;                                   //MSB
InstMem[15] = 8'b00000000;                                   //LSB
InstMem[16] = 8'b00000000;                                   //LSB
InstMem[17] = 8'b00000000;                                   //MSB 
InstMem[18] = 8'b00000000;                                   //LSB 
InstMem[19] = 8'b00000000;                                   //MSB

register[0] = 16'b0000000000000001;
register[1] = 16'b0000000000000010;
register[2] = 16'b0000000000000000;
register[3] = 16'b0000000000000000;
register[4] = 16'b0000000000000000;
register[5] = 16'b0000000000000000;
register[6] = 16'b0000000000000000;
register[7] = 16'b0000000000000000;

end

always@(decode26)
begin
ir235={InstMem[PC21+1],InstMem[PC21]};
case(ir235[15:12])
4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111, 4'b1000, 4'b1001:begin                //for arithematic 
rs1=ir235[11:9];
rs2=ir235[8:6];
wd=ir235[2:0];
rd23 = register[rs1];
rd2345 = register[rs2];
end

4'b0000, 4'b0001:begin                   //for LOAD, STORE
rs1=ir235[11:9];
rd23 = register[rs1];
case (ir235[7])
1'b0:temp214={10'b0000000000,ir235[5:0]};
1'b1:temp214={10'b1111111111,ir235[5:0]};
default:temp214={10'b0000000000,ir235[5:0]};
endcase
rd2345=ir235[8:6];
end

4'b1010, 4'b1011:begin                   //for BEQZ, BNEQZ
rs1=ir235[11:9];
rd23 = register[rs1];
rs2=ir235[8:6];
rd2345 = register[rs2];
case (ir235[7])
1'b0:temp214={10'b0000000000,ir235[5:0]};
1'b1:temp214={10'b1111111111,ir235[5:0]};
default:temp214={10'b0000000000,ir235[5:0]};
endcase
end

4'b1100:begin                             //for JUMP       
PCselect2136=2'b10;
fetch2136=fetch2136+1;
end

default:begin
rs1=ir235[11:9];
rs2=ir235[8:6];
wd=ir235[2:0];
end
endcase
end
endmodule