我看到同样的问题here,我试图按照这个例子,但在声明我的信号时遇到了错误。具体来说:
#Error: COMP96_0015: Pipeline.vhd : (52, 44): ';' expected.
这是我的代码:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Pipeline isgeneric (
VECTOR_WIDTH: natural := 128;
VECTOR_DEPTH: natural := 7
); port(
ImVal : in STD_LOGIC_VECTOR(9 downto 0);
RA : in STD_LOGIC_VECTOR(127 downto 0);
RB : in STD_LOGIC_VECTOR(127 downto 0);
RC : in STD_LOGIC_VECTOR(127 downto 0);
OpCode : in STD_LOGIC_VECTOR(10 downto 0);
RT : in STD_LOGIC_VECTOR(127 downto 0);
Clk: in STD_LOGIC;
Reset: in STD_LOGIC;
OutVal : out STD_LOGIC_VECTOR(127 downto 0)
);
end Pipeline;
architecture Behavioral of Pipeline is
type shift_reg_type1 is array (natural range<>) of std_logic_vector(127 downto 0);
type shift_reg_type2 is array (natural range<>) of std_logic_vector(10 downto 0);
type shift_reg_type3 is array (natural range<>) of std_logic_vector(9 downto 0);
signal shift_regA: shift_reg_type1(0 to 6)(127 downto 0);
signal shift_regB: shift_reg_type1(0 to 6)(127 downto 0);
signal shift_regC: shift_reg_type1(0 to 6)(127 downto 0);
signal shift_regT: shift_reg_type1(0 to 6)(127 downto 0);
signal OpCode_reg: shift_reg_type2(0 to 6)(10 downto 0);
signal ImVal_reg: shift_reg_type3(0 to 6)(9 downto 0);
begin
end Behavioral;
它抱怨我的信号声明,但我不明白为什么。
答案 0 :(得分:2)
错误消息说明信号声明错误。此外,它需要一个分号,因为语句已完成,但您的代码每个信号有两个范围限制......
signal shift_regA: shift_reg_type1(0 to 6);
signal shift_regB: shift_reg_type1(0 to 6);
signal shift_regC: shift_reg_type1(0 to 6);
signal shift_regT: shift_reg_type1(0 to 6);
signal OpCode_reg: shift_reg_type2(0 to 6);
signal ImVal_reg: shift_reg_type3(0 to 6);
shift_reg_type1
已经约束到127..0。因此,无法在第二维中再次约束shift_regA
。顺便说一句。没有第二个维度,因为它是一维元素的一维数组。